cpu87.h

linux下的BOOT程序原码,有需要的可以来下,保证好用

#endif
#else
/* environment is in EEPROM */
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
#define CFG_ENV_OFFSET		512
#define CFG_ENV_SIZE		(2048 - 512)
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM		0x02	/* Software reboot		   */


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers			 2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
			 HID0_DCI|HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL	(HID0_IFEM|HID0_ABE)
#define CFG_HID2	0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register					 5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR		RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration					 4-25
 *-----------------------------------------------------------------------
 */
#define BCR_APD01	0x10000000
#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				 4-31
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				 4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control			 4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control					 9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CFG_SCCR	SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration				13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR	0

#define CFG_MIN_AM_MASK 0xC0000000

/*
 * we use the same values for 32 MB and 128 MB SDRAM
 * refresh rate = 7.68 uS (100 MHz Bus Clock)
 */

/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register		10-18
 *-----------------------------------------------------------------------
 */
#define CFG_MPTPR	0x2000

/*-----------------------------------------------------------------------
 * PSRT - Refresh Timer Register				10-16
 *-----------------------------------------------------------------------
 */
#define CFG_PSRT	0x16

/*-----------------------------------------------------------------------
 * PSRT - SDRAM Mode Register					10-10
 *-----------------------------------------------------------------------
 */

	/* SDRAM initialization values for 8-column chips
	 */
#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI0_A9		|\
			 ORxS_NUMR_12)

#define CFG_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
			 PSDMR_BSMA_A14_A16		|\
			 PSDMR_SDA10_PBI0_A10		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_2W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI0_A7		|\
			 ORxS_NUMR_13)

#define CFG_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
			 PSDMR_BSMA_A13_A15		|\
			 PSDMR_SDA10_PBI0_A9		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_2W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

/*
 * Init Memory Controller:
 *
 * Bank Bus	Machine PortSz	Device
 * ---- ---	------- ------	------
 *  0	60x	GPCM	8  bit	Boot ROM
 *  1	60x	GPCM	64 bit	FLASH
 *  2	60x	SDRAM	64 bit	SDRAM
 *
 */

#define CFG_MRS_OFFS	0x00000000

#ifdef CONFIG_BOOT_ROM
/* Bank 0 - Boot ROM
 */
#define CFG_BR0_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_5_CLK			|\
			 ORxU_EHTR_8IDLE)

/* Bank 1 - FLASH
 */
#define CFG_BR1_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_5_CLK			|\
			 ORxU_EHTR_8IDLE)

#else /* CONFIG_BOOT_ROM */
/* Bank 0 - FLASH
 */
#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR0_PRELIM	(P2SZ_TO_AM(CFG_FLASH_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_5_CLK			|\
			 ORxU_EHTR_8IDLE)

/* Bank 1 - Boot ROM
 */
#define CFG_BR1_PRELIM	((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR1_PRELIM	(P2SZ_TO_AM(CFG_BOOTROM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_5_CLK			|\
			 ORxU_EHTR_8IDLE)

#endif /* CONFIG_BOOT_ROM */


/* Bank 2 - 60x bus SDRAM
 */
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM	((CFG_SDRAM_BASE & BRx_BA_MSK)	|\
			 BRx_PS_64			|\
			 BRx_MS_SDRAM_P			|\
			 BRx_V)

#define CFG_OR2_PRELIM	 CFG_OR2_9COL

#define CFG_PSDMR	 CFG_PSDMR_9COL
#endif /* CFG_RAMBOOT */

/* Bank 3 - Dual Ported SRAM
 */
#define CFG_BR3_PRELIM	((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
			 BRx_PS_16			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR3_PRELIM	(P2SZ_TO_AM(CFG_DPSRAM_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_7_CLK			|\
			 ORxG_SETA)

/* Bank 4 - DiskOnChip
 */
#define CFG_BR4_PRELIM	((CFG_DOC_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR4_PRELIM	(P2SZ_TO_AM(CFG_DOC_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV2			|\
			 ORxG_SCY_9_CLK			|\
			 ORxU_EHTR_8IDLE)

/* Bank 5 - FDC37C78 controller
 */
#define CFG_BR5_PRELIM	((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
			 BRx_PS_8			  |\
			 BRx_MS_GPCM_P			  |\
			 BRx_V)

#define CFG_OR5_PRELIM	(P2SZ_TO_AM(CFG_FDC37C78_SIZE)	  |\
			 ORxG_ACS_DIV2			  |\
			 ORxG_SCY_10_CLK		  |\
			 ORxU_EHTR_8IDLE)

/* Bank 6 - Board control registers
 */
#define CFG_BR6_PRELIM	((CFG_BCRS_BASE & BRx_BA_MSK)	|\
			 BRx_PS_8			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR6_PRELIM	(P2SZ_TO_AM(CFG_BCRS_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_SCY_7_CLK)

/* Bank 7 - VME Extended Access Range
 */
#define CFG_BR7_PRELIM	((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
			 BRx_PS_32			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR7_PRELIM	(P2SZ_TO_AM(CFG_VMEEAR_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_7_CLK			|\
			 ORxG_SETA)

/* Bank 8 - VME Standard Access Range
 */
#define CFG_BR8_PRELIM	((CFG_VMESAR_BASE & BRx_BA_MSK) |\
			 BRx_PS_16			|\
			 BRx_MS_GPCM_P			|\
			 BRx_V)

#define CFG_OR8_PRELIM	(P2SZ_TO_AM(CFG_VMESAR_SIZE)	|\
			 ORxG_CSNT			|\
			 ORxG_ACS_DIV1			|\
			 ORxG_SCY_7_CLK			|\
			 ORxG_SETA)

/* Bank 9 - VME Short I/O Access Range
 */
#define CFG_BR9_PRELIM	((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
			 BRx_PS_16			  |\
			 BRx_MS_GPCM_P			  |\
			 BRx_V)

#define CFG_OR9_PRELIM	(P2SZ_TO_AM(CFG_VMESIOAR_SIZE)	  |\
			 ORxG_CSNT			  |\
			 ORxG_ACS_DIV1			  |\
			 ORxG_SCY_7_CLK			  |\
			 ORxG_SETA)

#endif	/* __CONFIG_H */