📄 f243sci3.c
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/************************************************************************/
/* Testprogram for serial communication SCI */
/* running on TMS320F243 EVA-Board, PLL is fixed to multiply by 4 */
/* external clock is 5MHz, internal then 20Mhz */
/* date : 07/14/2000 , (C) Frank.Bormann@fh-zwickau.de */
/************************************************************************/
/* SCI-communication RS232 from EVA-board to PC- COM1 or COM2 */
/* Receiving from Windows-95 Hyperterminal-Session */
/* write a textfile containing a one line text and a <CR> and send this */
/* file by Hyperterminal to the F243 ( "Transmission - Text file" ) */
/* 9600 Baud , 8bit, no parity , 1 Stopbit , no protocol */
/* The F243 monitors the receiver by its interrupt service routine, when*/
/* the received character was a <CR> the string 'READY' is transmitted */
/* uses both TXD-interrupt- and RXD-interrupt-service */
/* program-name : F243SCI3.c / project : F243SCI3 */
/************************************************************************/
#include "regs243.h"
/************* SETUP for the OCRA - Register **************/
#define OCRA15 0 /* 0 : IOPB7 1 : TCLKIN */
#define OCRA14 0 /* 0 : IOPB6 1 : TDIR */
#define OCRA13 0 /* 0 : IOPB5 1 : T2PWM */
#define OCRA12 0 /* 0 : IOPB4 1 : T1PWM */
#define OCRA11 0 /* 0 : IOPB3 1 : PWM6 */
#define OCRA10 0 /* 0 : IOPB2 1 : PWM5 */
#define OCRA9 0 /* 0 : IOPB1 1 : PWM4 */
#define OCRA8 0 /* 0 : IOPB0 1 : PWM3 */
#define OCRA7 0 /* 0 : IOPA7 1 : PWM2 */
#define OCRA6 0 /* 0 : IOPA6 1 : PWM1 */
#define OCRA5 0 /* 0 : IOPA5 1 : CAP3 */
#define OCRA4 0 /* 0 : IOPA4 1 : CAP2/QEP2 */
#define OCRA3 0 /* 0 : IOPA3 1 : CAP1/QEP1 */
#define OCRA2 0 /* 0 : IOPA2 1 : XINT1 */
#define OCRA1 1 /* 0 : IOPA1 1 : SCIRXD */
#define OCRA0 1 /* 0 : IOPA0 1 : SCITXD */
/****************************************************************/
/************* SETUP for the OCRB - Register **************/
#define OCRB9 0 /* 0 : IOPD1 1 : XINT2/EXTSOC */
#define OCRB8 1 /* 0 : CKLKOUT 1 : IOPD0 */
#define OCRB7 0 /* 0 : IOPC7 1 : CANRX */
#define OCRB6 0 /* 0 : IOPC6 1 : CANTX */
#define OCRB5 0 /* 0 : IOPC5 1 : SPISTE */
#define OCRB4 0 /* 0 : IOPC4 1 : SPICLK */
#define OCRB3 0 /* 0 : IOPC3 1 : SPISOMI */
#define OCRB2 0 /* 0 : IOPC2 1 : SPISIMO */
#define OCRB1 1 /* 0 : BIO 1 : IOPC1 */
#define OCRB0 1 /* 0 : XF 1 : IOPC0 */
/****************************************************************/
/************* SETUP for the WDCR - Register **************/
#define WDDIS 1 /* 0 : Watchdog enabled 1: disabled */
#define WDCHK2 1 /* 0 : System reset 1: Normal OP */
#define WDCHK1 0 /* 0 : Normal Oper. 1: sys reset */
#define WDCHK0 1 /* 0 : System reset 1: Normal OP */
#define WDSP 7 /* Watchdog prescaler 7 : div 64 */
/****************************************************************/
/************* SETUP for the SCSR - Register **************/
#define CLKSRC 0 /* 0 : intern(20MHz) */
#define LPM 0 /* 0 : Low power mode 0 if idle */
#define ILLADR 1 /* 1 : clear illegal address flag */
/****************************************************************/
/************* SETUP for the WSGR - Register **************/
#define BVIS 0 /* 10-9 : 00 Bus visibility OFF */
#define ISWS 0 /* 8 -6 : 000 0 Waitstates for IO */
#define DSWS 0 /* 5 -3 : 000 0 Waitstates data */
#define PSWS 0 /* 2 -0 : 000 0 Waitstaes code */
/****************************************************************/
/************* SETUP for the EVIMRA - Register *************/
#define T1OFINT 0 /* 10 : Timer 1 overflow interrupt */
#define T1UFINT 0 /* 9 : Timer 1 underflow interrupt */
#define T1CINT 0 /* 8 : Timer 1 compare interrupt */
#define T1PINT 0 /* 7 : Timer 1 period interrupt */
#define CMP3INT 0 /* 3 : Compare 3 interrupt */
#define CMP2INT 0 /* 2 : Compare 2 interrupt */
#define CMP1INT 0 /* 1 : Compare 1 interrupt */
#define PDPINT 0 /* 0 : Power Drive Protect Interrupt*/
/****************************************************************/
/************* SETUP for the EVIMRB - Register *************/
#define T2OFINT 0 /* 3 : Timer 2 overflow interrupt */
#define T2UFINT 0 /* 2 : Timer 2 underflow interrupt */
#define T2CINT 0 /* 1 : Timer 2 compare interrupt */
#define T2PINT 0 /* 0 : Timer 2 period interrupt */
/****************************************************************/
/************* SETUP for the EVIMRC- Register **************/
#define CAP3INT 0 /* 2 : Capture Unit 3 interrupt */
#define CAP2INT 0 /* 1 : Capture Unit 2 Interrupt */
#define CAP1INT 0 /* 0 : Capture unit 1 interrupt */
/****************************************************************/
/************* SETUP for the IMR - Register **************/
#define INT6 0 /* 5 : Level INT6 is masked */
#define INT5 0 /* 4 : Level INT5 is masked */
#define INT4 0 /* 3 : Level INT4 is masked */
#define INT3 0 /* 2 : Level INT3 is masked */
#define INT2 0 /* 1 : Level INT2 is masked */
#define INT1 1 /* 0 : Level INT1 is unmasked */
/****************************************************************/
/************* SETUP for the SCICCR - Register **************/
#define STOPBITS 0 /* 0 : one stop bit */
#define EVENODD 0 /* 0 : odd parity */
#define PARITY 0 /* 0 : no parity */
#define LOOPBACKENA 0 /* 0 : Loop Back Test Mode disabled*/
#define ADDRIDLE 0 /* 0 : IDLE-line mode for multipr. */
#define SCICHAR 7 /* 111 : 8-bit data transmission */
/****************************************************************/
/************* SETUP for the SCICTL1 - Register *************/
#define RXERRINT 0 /* 0 : disable Rx Error Interrupts */
#define SWRESET 0 /* 0 : apply reset state */
/* 1 : reenabling SCI, after config.*/
#define TXWAKE 0 /* 0 : no wakeupfunction now */
#define SLEEP 0 /* 0 : sleep mode disabled */
#define TXENA 1 /* 1 : Transmitter enabled */
#define RXENA 1 /* 1 : Receiver enabled */
/****************************************************************/
/************* SETUP for the SCICTL2 - Register *************/
#define RXBKINT 1 /* 0 : enable RX and Break inter. */
#define TXINT 1 /* 1 : enable TXRDY-interrupt */
/****************************************************************/
/************* SETUP for the SCIPRI - Register **************/
#define TXPRIORITY 0 /* TXD-int on high Priority (INT1) */
#define RXPRIORITY 0 /* RXD-int on high Priority (INT1) */
#define SCISOFTFREE 2 /* on emulator suspend complete SCI */
/****************************************************************/
#define BRR 259 /* baudrate register constant
/* 259 = (20e+6/(9600Baud *8)) -1 */
static char index=0;
const char message[7]="READY\n\r";
interrupt void SCI_ISR(void);
void c_dummy1(void);
extern _out_wsgr();
void c_dummy1(void)
{
while(1); /*Dummy ISR used to trap spurious interrupts*/
}
interrupt void SCI_ISR(void)
{
if((PIVR-0x0007)==0) /*Verify type of interrupt ( 7 = TxD ) */
{
if(index<=6) SCITXBUF=message[index++]; /* Transmit next byte */
else index=0; /* reset message pointer */
}
if((PIVR-0x0006)==0) /* 6 = receiver interrupt */
{
if(SCIRXBUF==0x0D) SCITXBUF=message[index++];
/* when <CR> received then start transmission */
}
}
void main(void)
{
asm (" setc INTM");/*Disable all interrupts */
asm (" clrc SXM"); /*Clear Sign Extension Mode bit */
asm (" clrc OVM"); /*Reset Overflow Mode bit*/
asm (" clrc CNF"); /*Configure block B0 to data mem. */
WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);
/* Initialize Watchdog-timer */
SCSR = ((CLKSRC<<14)+(LPM<<12)+ILLADR); /* Initialize SCSR */
out_wsgr((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS);
/* external Function for access WSGR */
OCRB = ((OCRB9<<9)+(OCRB8<<8)+
(OCRB7<<7)+(OCRB6<<6)+(OCRB5<<5)+(OCRB4<<4)+
(OCRB3<<3)+(OCRB2<<2)+(OCRB1<<1)+OCRB0);
/* Initialize output control register B */
OCRA = ((OCRA15<<15)+(OCRA14<<14)+(OCRA13<<13)+(OCRA12<<12)+
(OCRA11<<11)+(OCRA10<<10)+(OCRA9<<9)+(OCRA8<<8)+
(OCRA7<<7)+(OCRA6<<6)+(OCRA5<<5)+(OCRA4<<4)+
(OCRA3<<3)+(OCRA2<<2)+(OCRA1<<1)+OCRA0);
/* Initialize output control register A */
SCICCR=((STOPBITS<<7)+(EVENODD<<6)+(PARITY<<5)+
(LOOPBACKENA<<4)+(ADDRIDLE<<3)+SCICHAR);
/* Initialize SCI Control Register */
SCICTL1=((RXERRINT<<6)+(SWRESET<<5)+
(TXWAKE<<3)+(SLEEP<<2)+(TXENA<<1)+RXENA);
/* initialize SCI Control Register 1 */
SCICTL2=((RXBKINT<<1)+TXINT);
/* initialize SCI Control Register 2 */
SCIHBAUD=BRR>>8; /* load the Baud-select register */
SCILBAUD=BRR & 0x00FF;
SCIPRI= ((TXPRIORITY<<6)+(RXPRIORITY<<5)+(SCISOFTFREE<<3));
/* Initialize SCI Priority control register */
SCICTL1|=0x0020; /* reenable SCI , SWRESET=1 */
EVIFRA=0xFFFF; /* clear EV Interrupt Flag Register Group A */
EVIFRB=0xFFFF; /* clear EV Interrupt Flag Register Group B */
EVIFRC=0xFFFF; /* clear EV Interupt Flag Register Group C */
EVIMRA=((T1OFINT<<10)+
(T1UFINT<<9)+
(T1CINT<<8)+
(T1PINT<<7)+
(CMP3INT<<3)+
(CMP2INT<<2)+
(CMP1INT<<1)+
(PDPINT)); /* enable EV Interrupt Mask Register Group A */
EVIMRB=((T2OFINT<<3)+
(T2UFINT<<2)+
(T2CINT<<1)+
(T2PINT)); /* enable EV Interrupt Mask Register Group B */
EVIMRC=((CAP3INT<<2)+
(CAP2INT<<1)+
(CAP1INT)); /* enable EV Interrupt Mask Register Group C */
IFR=0xFFFF; /* Reset all core interrupts */
IMR=((INT6<<5)+
(INT5<<4)+
(INT4<<3)+
(INT3<<2)+
(INT2<<1)+
(INT1)); /* enable core Interrupts */
asm (" clrc INTM"); /* Enable all unmasked interrupts */
while(1); /* endless loop ; action done by ISR */
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