bp2.tan.qmsg

在FPGA或CPLD上实现的一中非常实用的倍频电路

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register d register e 100.0 MHz 10.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 100.0 MHz between source register \"d\" and destination register \"e\" (period= 10.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d 1 REG LC1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'd'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { d } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns e 2 REG LC5 2 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'e'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.000 ns" { d e } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 83.33 % ) " "Info: Total cell delay = 5.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 1.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.000 ns" { d e } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.000 ns" { d e } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { clk } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns e 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC5; Fanout = 2; REG Node = 'e'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "0.000 ns" { clk e } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk e } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out e } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { clk } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns d 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 3; REG Node = 'd'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "0.000 ns" { clk d } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk d } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out d } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk e } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out e } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk d } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out d } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.000 ns" { d e } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.000 ns" { d e } { 0.000ns 1.000ns } { 0.000ns 5.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk e } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out e } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk d } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out d } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "b indata clk 7.000 ns register " "Info: tsu for register \"b\" (data pin = \"indata\", clock pin = \"clk\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns indata 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'indata'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { indata } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns b 2 REG LC2 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'b'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.000 ns" { indata b } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.500 ns" { indata b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.500 ns" { indata indata~out b } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { clk } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns b 2 REG LC2 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'b'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "0.000 ns" { clk b } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out b } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.500 ns" { indata b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.500 ns" { indata indata~out b } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out b } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y d 13.000 ns register " "Info: tco from clock \"clk\" to destination pin \"y\" through register \"d\" is 13.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { clk } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns d 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 3; REG Node = 'd'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "0.000 ns" { clk d } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk d } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out d } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.500 ns + Longest register pin " "Info: + Longest register to pin delay is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d 1 REG LC1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'd'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { d } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(7.000 ns) 8.000 ns y~5 2 COMB LC3 1 " "Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'y~5'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "8.000 ns" { d y~5 } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 9.500 ns y 3 PIN PIN_12 0 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'y'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { y~5 y } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns ( 89.47 % ) " "Info: Total cell delay = 8.500 ns ( 89.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 10.53 % ) " "Info: Total interconnect delay = 1.000 ns ( 10.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "9.500 ns" { d y~5 y } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "9.500 ns" { d y~5 y } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk d } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out d } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "9.500 ns" { d y~5 y } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "9.500 ns" { d y~5 y } { 0.000ns 1.000ns 0.000ns } { 0.000ns 7.000ns 1.500ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "b indata clk -2.000 ns register " "Info: th for register \"b\" (data pin = \"indata\", clock pin = \"clk\") is -2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { clk } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns b 2 REG LC2 3 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'b'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "0.000 ns" { clk b } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out b } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "3.000 ns + " "Info: + Micro hold delay of destination is 3.000 ns" {  } { { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns indata 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'indata'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "" { indata } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns b 2 REG LC2 3 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC2; Fanout = 3; REG Node = 'b'" {  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.000 ns" { indata b } "NODE_NAME" } "" } } { "bp2.vhd" "" { Text "D:/fpga/bp2/bp2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.500 ns" { indata b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.500 ns" { indata indata~out b } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "1.500 ns" { clk b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "1.500 ns" { clk clk~out b } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51sp1/bin/Report_Window_01.qrpt" "Compiler" "bp2" "UNKNOWN" "V1" "D:/fpga/bp2/db/bp2.quartus_db" { Floorplan "D:/fpga/bp2/" "" "6.500 ns" { indata b } "NODE_NAME" } "" } } { "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51sp1/bin/Technology_Viewer.qrui" "6.500 ns" { indata indata~out b } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 24 23:17:18 2006 " "Info: Processing ended: Mon Apr 24 23:17:18 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}