bp2.map.qmsg

在FPGA或CPLD上实现的一中非常实用的倍频电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 24 23:17:46 2006 " "Info: Processing started: Mon Apr 24 23:17:46 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off bp2 -c bp2 --generate_symbol=D:\\fpga\\bp2\\bp2.vhd " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bp2 -c bp2 --generate_symbol=D:\\fpga\\bp2\\bp2.vhd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 24 23:17:46 2006 " "Info: Processing ended: Mon Apr 24 23:17:46 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}