bp2.tan.talkback.xml

在FPGA或CPLD上实现的一中非常实用的倍频电路

<!--
This XML file (created on Mon Apr 24 23:17:18 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_213.xsd</schema><license>
	<host_id>000f1fcdee18</host_id>
	<nic_id>000f1fcdee18</nic_id>
	<cdrive_id>ec332b21</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 213</build>
	<service_pack_label>1</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Mon Apr 24 23:17:18 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1593</cpu_freq>
	</cpu>
	<ram units="MB">511</ram>
</machine>
<top_file>D:/fpga/bp2/bp2</top_file>
<compilation_summary>
	<flow_status>Successful - Mon Apr 24 23:17:18 2006</flow_status>
	<quartus_ii_version>5.1 Build 213 01/19/2006 SP 1 SJ Web Edition</quartus_ii_version>
	<revision_name>bp2</revision_name>
	<top_level_entity_name>bp2</top_level_entity_name>
	<family>MAX7000S</family>
	<device>EPM7128SLC84-10</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_macrocells>5 / 128 ( 4 % )</total_macrocells>
	<total_pins>8 / 68 ( 12 % )</total_pins>
</compilation_summary>
<compile_id>81075B6C</compile_id>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off bp2 -c bp2</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Mon Apr 24 23:17:18 2006</info>
	<info>Info: th for register &quot;b&quot; (data pin = &quot;indata&quot;, clock pin = &quot;clk&quot;) is -2.000 ns</info>
	<info>Info: - Shortest pin to register delay is 6.500 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>13.000 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>-2.000 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>100.00 MHz ( period = 10.000 ns )</actual>
	</clk>
</performance>
<compile_id>782BCC66</compile_id>
</talkback>