bp2.sim.talkback.xml

在FPGA或CPLD上实现的一中非常实用的倍频电路

<!--
This XML file (created on Fri Apr 28 21:54:26 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_213.xsd</schema><license>
	<nic_id>0015c50f2ef8</nic_id>
	<cdrive_id>64d67f40</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 213</build>
	<service_pack_label>1</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Fri Apr 28 21:54:26 2006</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1828</cpu_freq>
	</cpu>
	<ram units="MB">1015</ram>
</machine>
<top_file>D:/fpga/bp2/bp2</top_file>
<compilation_summary>
	<flow_status>Successful - Fri Apr 28 21:54:26 2006</flow_status>
	<simulator_setting_name>bp2</simulator_setting_name>
	<top_level_entity_name>bp2</top_level_entity_name>
</compilation_summary>
<compile_id>4422ABB8</compile_id>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off bp2 -c bp2</command_line>
</mep_data>
<messages>
	<warning>Warning: Found glitch at time 0.5 ns of duration 0.5 ns on node &quot;|bp2|indatb&quot;</warning>
	<warning>Warning: Found glitch at time 0.5 ns of duration 0.5 ns on node &quot;|bp2|indata&quot;</warning>
	<info>Info: Quartus II Simulator was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Fri Apr 28 21:54:26 2006</info>
	<info>Info: Number of transitions in simulation is 11398</info>
	<info>Info: Simulation coverage is     100.00 %</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Vector input source</option>
		<setting>bp2.vwf</setting>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>On</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Glitch interval</option>
		<setting units="ns">1</setting>
		<default_value units="ns">1</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>Off</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>Off</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>50.0 us</simulation_end_time>
	<simulation_netlist_size>9 nodes</simulation_netlist_size>
	<simulation_coverage>    100.00 %</simulation_coverage>
	<total_number_of_transitions>11398</total_number_of_transitions>
	<family>MAX7000S</family>
	<device>EPM7128SLC84-10</device>
</simulator_summary>
<compile_id>115FCBDD</compile_id>
</talkback>