div.rpt

用cpld开发的激光控制器的源码

Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                    d:\laserinterface\cpld\div.rpt
div

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  73    115    H         FF   +  t        0      0   0    0    3    0    0  compare (:7)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                    d:\laserinterface\cpld\div.rpt
div

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -    113    H       DFFE   +  t        0      0   0    0    3    1    1  cnt2 (:4)
   -    114    H       DFFE   +  t        0      0   0    0    2    1    2  cnt1 (:5)
   -    116    H       TFFE   +  t        0      0   0    0    0    1    2  cnt0 (:6)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                    d:\laserinterface\cpld\div.rpt
div

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                 Logic cells placed in LAB 'H'
        +------- LC115 compare
        | +----- LC113 cnt2
        | | +--- LC114 cnt1
        | | | +- LC116 cnt0
        | | | | 
        | | | |   Other LABs fed by signals
        | | | |   that feed LAB 'H'
LC      | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC113-> * * - - | - - - - - - - * | <-- cnt2
LC114-> * * * - | - - - - - - - * | <-- cnt1
LC116-> * * * * | - - - - - - - * | <-- cnt0

Pin
83   -> - - - - | - - - - - - - - | <-- clk_input


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    d:\laserinterface\cpld\div.rpt
div

** EQUATIONS **

clk_input : INPUT;

-- Node name is ':6' = 'cnt0' 
-- Equation name is 'cnt0', location is LC116, type is buried.
cnt0     = TFFE( VCC, GLOBAL( clk_input),  VCC,  VCC,  VCC);

-- Node name is ':5' = 'cnt1' 
-- Equation name is 'cnt1', location is LC114, type is buried.
cnt1     = DFFE( _EQ001 $  GND, GLOBAL( clk_input),  VCC,  VCC,  VCC);
  _EQ001 = !cnt0 &  cnt1
         #  cnt0 & !cnt1;

-- Node name is ':4' = 'cnt2' 
-- Equation name is 'cnt2', location is LC113, type is buried.
cnt2     = DFFE( _EQ002 $  GND, GLOBAL( clk_input),  VCC,  VCC,  VCC);
  _EQ002 =  cnt0 &  cnt1 & !cnt2
         # !cnt0 &  cnt2
         # !cnt1 &  cnt2;

-- Node name is 'compare' = 'compare_temp' 
-- Equation name is 'compare', location is LC115, type is output.
 compare = TFFE(!_EQ003, GLOBAL( clk_input),  VCC,  VCC,  VCC);
  _EQ003 =  cnt2
         #  cnt1
         #  cnt0;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             d:\laserinterface\cpld\div.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,020K