📄 sine_32.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sine_32 is
port(clk,rst: in std_logic;
q_3: out std_logic;
sel:in std_logic;
data_out: out std_logic_vector(7 downto 0));
end sine_32;
architecture behav of sine_32 is
signal cnt: integer range 0 to 31;
signal cnt_temp: std_logic_vector(4 downto 0);
signal temp_dataout: integer range 0 to 255;
begin
process(clk,rst)
begin
if rst='1' then cnt<= 0;
elsif clk'event and clk='1' then
if cnt=31 then cnt<=0;
else cnt <= cnt+1;
end if;
end if;
end process;
process(cnt) is
begin
if sel='0' then
case cnt is
when 0 => temp_dataout<=127;
when 1 => temp_dataout<=152;
when 2 => temp_dataout<=176;
when 3 => temp_dataout<=197;
when 4 => temp_dataout<=217;
when 5 => temp_dataout<=233;
when 6 => temp_dataout<=244;
when 7 => temp_dataout<=252;
when 8 => temp_dataout<=254;
when 9 => temp_dataout<=252;
when 10 => temp_dataout<=244;
when 11 => temp_dataout<=233;
when 12 => temp_dataout<=217;
when 13 => temp_dataout<=197;
when 14 => temp_dataout<=176;
when 15 => temp_dataout<=152;
when 16 => temp_dataout<=127;
when 17 => temp_dataout<=102;
when 18 => temp_dataout<=78;
when 19 => temp_dataout<=57;
when 20 => temp_dataout<=37;
when 21 => temp_dataout<=21;
when 22 => temp_dataout<=10;
when 23 => temp_dataout<=02;
when 24 => temp_dataout<=0;
when 25 => temp_dataout<=02;
when 26 => temp_dataout<=10;
when 27 => temp_dataout<=21;
when 28 => temp_dataout<=37;
when 29 => temp_dataout<=57;
when 30 => temp_dataout<=78;
when 31 => temp_dataout<=102;
when others=>temp_dataout<=0;
end case;
else
case cnt is
when 0 => temp_dataout<=127;
when 1 => temp_dataout<=102;
when 2 => temp_dataout<=78;
when 3 => temp_dataout<=57;
when 4 => temp_dataout<=37;
when 5 => temp_dataout<=21;
when 6 => temp_dataout<=10;
when 7 => temp_dataout<=02;
when 8 => temp_dataout<=0;
when 9 => temp_dataout<=02;
when 10 => temp_dataout<=10;
when 11 => temp_dataout<=21;
when 12 => temp_dataout<=37;
when 13 => temp_dataout<=57;
when 14 => temp_dataout<=78;
when 15 => temp_dataout<=102;
when 16 => temp_dataout<=127;
when 17 => temp_dataout<=152;
when 18 => temp_dataout<=176;
when 19 => temp_dataout<=197;
when 20 => temp_dataout<=217;
when 21 => temp_dataout<=233;
when 22 => temp_dataout<=244;
when 23 => temp_dataout<=252;
when 24 => temp_dataout<=254;
when 25 => temp_dataout<=252;
when 26 => temp_dataout<=244;
when 27 => temp_dataout<=233;
when 28 => temp_dataout<=217;
when 29 => temp_dataout<=197;
when 30 => temp_dataout<=176;
when 31 => temp_dataout<=152;
when others=>temp_dataout<=0;
end case;
end if;
end process;
cnt_temp <= conv_std_logic_vector(cnt,5);
q_3 <= cnt_temp(3);
data_out <= conv_std_logic_vector(temp_dataout,8);
end behav;
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