📄 composite.rpt
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_X003 = EXP( _LC024 & !_LC026 & !_LC027 & !q_3);
-- Node name is 'data_out3' = '|SINE_32:22|:2035'
-- Equation name is 'data_out3', type is output
data_out3 = LCELL( _EQ006 $ !_LC027);
_EQ006 = !_LC024 & _LC026
# !_LC023 & _LC026 & !q_3
# !_LC023 & !_LC024 & _LC027 & !q_3
# _LC023 & _LC024 & !_LC026 & q_3;
-- Node name is 'data_out4' = '|SINE_32:22|:1939'
-- Equation name is 'data_out4', type is output
data_out4 = LCELL( _EQ007 $ !_LC027);
_EQ007 = !_LC023 & _LC024 & _LC026
# _LC023 & _LC024 & !_LC026
# !_LC023 & !_LC024 & !_LC026 & _LC027 & !q_3;
-- Node name is 'data_out5' = '|SINE_32:22|:1843'
-- Equation name is 'data_out5', type is output
data_out5 = LCELL( _EQ008 $ !_LC027);
_EQ008 = _LC023 & !_LC024 & !_LC026
# !_LC023 & _LC024 & !q_3
# _LC023 & _LC024 & q_3
# !_LC023 & !_LC026 & _LC027 & !q_3;
-- Node name is 'data_out6' = '|SINE_32:22|:1747'
-- Equation name is 'data_out6', type is output
data_out6 = LCELL( _EQ009 $ !_LC027);
_EQ009 = _LC023 & _LC026 & q_3
# !_LC023 & _LC024 & !_LC026 & !q_3
# !_LC023 & !_LC024 & _LC026 & !q_3
# !_LC023 & !_LC024 & _LC027 & !q_3;
-- Node name is 'data_out7' = '|SINE_32:22|:1653'
-- Equation name is 'data_out7', type is output
data_out7 = LCELL( _EQ010 $ GND);
_EQ010 = !_LC027 & q_3
# _LC026 & !_LC027
# _LC024 & !_LC027
# _LC023 & !_LC027;
-- Node name is 'laser_pulse_ttl' = ':28'
-- Equation name is 'laser_pulse_ttl', type is output
laser_pulse_ttl = LCELL( laser_pulse_lvds $ GND);
-- Node name is 'q00' = '|decoder_latch:1|74373:49|:12'
-- Equation name is 'q00', type is output
q00 = LCELL( _EQ011 $ GND);
_EQ011 = pdata0 & q00
# !adress_0 & !adress_1 & pdata0 & wrrd
# adress_0 & q00
# q00 & !wrrd
# adress_1 & q00;
-- Node name is 'q01' = '|decoder_latch:1|74373:49|:13'
-- Equation name is 'q01', type is output
q01 = LCELL( _EQ012 $ GND);
_EQ012 = pdata1 & q01
# !adress_0 & !adress_1 & pdata1 & wrrd
# adress_0 & q01
# q01 & !wrrd
# adress_1 & q01;
-- Node name is 'q02' = '|decoder_latch:1|74373:49|:14'
-- Equation name is 'q02', type is output
q02 = LCELL( _EQ013 $ GND);
_EQ013 = pdata2 & q02
# !adress_0 & !adress_1 & pdata2 & wrrd
# adress_0 & q02
# q02 & !wrrd
# adress_1 & q02;
-- Node name is 'q03' = '|decoder_latch:1|74373:49|:15'
-- Equation name is 'q03', type is output
q03 = LCELL( _EQ014 $ GND);
_EQ014 = pdata3 & q03
# !adress_0 & !adress_1 & pdata3 & wrrd
# adress_0 & q03
# q03 & !wrrd
# adress_1 & q03;
-- Node name is 'q_3' = '|SINE_32:22|cnt3'
-- Equation name is 'q_3', type is output
q_3 = DFFE( _EQ015 $ GND, GLOBAL( sine_clk), !sine_rst, VCC, VCC);
_EQ015 = _LC023 & _LC024 & _LC026 & !q_3
# !_LC023 & q_3
# !_LC026 & q_3
# !_LC024 & q_3;
-- Node name is 'q04' = '|decoder_latch:1|74373:49|:16'
-- Equation name is 'q04', type is output
q04 = LCELL( _EQ016 $ GND);
_EQ016 = pdata4 & q04
# !adress_0 & !adress_1 & pdata4 & wrrd
# adress_0 & q04
# q04 & !wrrd
# adress_1 & q04;
-- Node name is 'q05' = '|decoder_latch:1|74373:49|:17'
-- Equation name is 'q05', type is output
q05 = LCELL( _EQ017 $ GND);
_EQ017 = pdata5 & q05
# !adress_0 & !adress_1 & pdata5 & wrrd
# adress_0 & q05
# q05 & !wrrd
# adress_1 & q05;
-- Node name is 'q06' = '|decoder_latch:1|74373:49|:18'
-- Equation name is 'q06', type is output
q06 = LCELL( _EQ018 $ GND);
_EQ018 = pdata6 & q06
# !adress_0 & !adress_1 & pdata6 & wrrd
# adress_0 & q06
# q06 & !wrrd
# adress_1 & q06;
-- Node name is 'q07' = '|decoder_latch:1|74373:49|:19'
-- Equation name is 'q07', type is output
q07 = LCELL( _EQ019 $ GND);
_EQ019 = pdata7 & q07
# !adress_0 & !adress_1 & pdata7 & wrrd
# adress_0 & q07
# q07 & !wrrd
# adress_1 & q07;
-- Node name is 'q10' = '|decoder_latch:1|74373:53|:12'
-- Equation name is 'q10', type is output
q10 = LCELL( _EQ020 $ GND);
_EQ020 = pdata0 & q10
# adress_0 & !adress_1 & pdata0 & wrrd
# !adress_0 & q10
# q10 & !wrrd
# adress_1 & q10;
-- Node name is 'q11' = '|decoder_latch:1|74373:53|:13'
-- Equation name is 'q11', type is output
q11 = LCELL( _EQ021 $ GND);
_EQ021 = pdata1 & q11
# adress_0 & !adress_1 & pdata1 & wrrd
# !adress_0 & q11
# q11 & !wrrd
# adress_1 & q11;
-- Node name is 'q12' = '|decoder_latch:1|74373:53|:14'
-- Equation name is 'q12', type is output
q12 = LCELL( _EQ022 $ GND);
_EQ022 = pdata2 & q12
# adress_0 & !adress_1 & pdata2 & wrrd
# !adress_0 & q12
# q12 & !wrrd
# adress_1 & q12;
-- Node name is 'q13' = '|decoder_latch:1|74373:53|:15'
-- Equation name is 'q13', type is output
q13 = LCELL( _EQ023 $ GND);
_EQ023 = pdata3 & q13
# adress_0 & !adress_1 & pdata3 & wrrd
# !adress_0 & q13
# q13 & !wrrd
# adress_1 & q13;
-- Node name is 'q14' = '|decoder_latch:1|74373:53|:16'
-- Equation name is 'q14', type is output
q14 = LCELL( _EQ024 $ GND);
_EQ024 = pdata4 & q14
# adress_0 & !adress_1 & pdata4 & wrrd
# !adress_0 & q14
# q14 & !wrrd
# adress_1 & q14;
-- Node name is 'q15' = '|decoder_latch:1|74373:53|:17'
-- Equation name is 'q15', type is output
q15 = LCELL( _EQ025 $ GND);
_EQ025 = pdata5 & q15
# adress_0 & !adress_1 & pdata5 & wrrd
# !adress_0 & q15
# q15 & !wrrd
# adress_1 & q15;
-- Node name is 'q16' = '|decoder_latch:1|74373:53|:18'
-- Equation name is 'q16', type is output
q16 = LCELL( _EQ026 $ GND);
_EQ026 = pdata6 & q16
# adress_0 & !adress_1 & pdata6 & wrrd
# !adress_0 & q16
# q16 & !wrrd
# adress_1 & q16;
-- Node name is 'q17' = '|decoder_latch:1|74373:53|:19'
-- Equation name is 'q17', type is output
q17 = LCELL( _EQ027 $ GND);
_EQ027 = pdata7 & q17
# adress_0 & !adress_1 & pdata7 & wrrd
# !adress_0 & q17
# q17 & !wrrd
# adress_1 & q17;
-- Node name is 'signal_out' = ':3'
-- Equation name is 'signal_out', type is output
signal_out = LCELL( coder_b $ coder_a);
-- Node name is '|DIV:2|:6' = '|DIV:2|cnt0'
-- Equation name is '_LC030', type is buried
_LC030 = TFFE( VCC, GLOBAL( pulse_ttl), VCC, VCC, VCC);
-- Node name is '|DIV:2|:5' = '|DIV:2|cnt1'
-- Equation name is '_LC113', type is buried
_LC113 = DFFE( _EQ028 $ GND, GLOBAL( pulse_ttl), VCC, VCC, VCC);
_EQ028 = !_LC030 & _LC113
# _LC030 & !_LC113;
-- Node name is '|DIV:2|:4' = '|DIV:2|cnt2'
-- Equation name is '_LC122', type is buried
_LC122 = DFFE( _EQ029 $ GND, GLOBAL( pulse_ttl), VCC, VCC, VCC);
_EQ029 = _LC030 & _LC113 & !_LC122
# !_LC030 & _LC122
# !_LC113 & _LC122;
-- Node name is '|SINE_32:22|:17' = '|SINE_32:22|cnt0'
-- Equation name is '_LC024', type is buried
_LC024 = TFFE( VCC, GLOBAL( sine_clk), !sine_rst, VCC, VCC);
-- Node name is '|SINE_32:22|:16' = '|SINE_32:22|cnt1'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( _EQ030 $ GND, GLOBAL( sine_clk), !sine_rst, VCC, VCC);
_EQ030 = _LC024 & !_LC026
# !_LC024 & _LC026;
-- Node name is '|SINE_32:22|:15' = '|SINE_32:22|cnt2'
-- Equation name is '_LC023', type is buried
_LC023 = DFFE( _EQ031 $ GND, GLOBAL( sine_clk), !sine_rst, VCC, VCC);
_EQ031 = !_LC023 & _LC024 & _LC026
# _LC023 & !_LC026
# _LC023 & !_LC024;
-- Node name is '|SINE_32:22|:13' = '|SINE_32:22|cnt4'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( _EQ032, GLOBAL( sine_clk), !sine_rst, VCC, VCC);
_EQ032 = _LC023 & _LC024 & _LC026 & q_3;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\laserinterface\cpld\composite.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 6,056K
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