📄 composite.rpt
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28 40 C OUTPUT t 1 0 1 4 1 1 0 q04
29 38 C OUTPUT t 1 0 1 4 1 1 0 q05
30 37 C OUTPUT t 1 0 1 4 1 1 0 q06
31 35 C OUTPUT t 1 0 1 4 1 1 0 q07
33 64 D OUTPUT t 1 0 1 4 1 1 0 q10
34 61 D OUTPUT t 1 0 1 4 1 1 0 q11
35 59 D OUTPUT t 1 0 1 4 1 1 0 q12
36 57 D OUTPUT t 1 0 1 4 1 1 0 q13
37 56 D OUTPUT t 1 0 1 4 1 1 0 q14
39 53 D OUTPUT t 1 0 1 4 1 1 0 q15
40 51 D OUTPUT t 1 0 1 4 1 1 0 q16
41 49 D OUTPUT t 1 0 1 4 1 1 0 q17
81 128 H OUTPUT t 0 0 0 2 0 0 0 signal_out
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 122 H DFFE + t 0 0 0 0 3 1 1 |DIV:2|cnt2 (|DIV:2|:4)
- 113 H DFFE + t 0 0 0 0 2 1 2 |DIV:2|cnt1 (|DIV:2|:5)
- 30 B TFFE + t 0 0 0 0 0 1 2 |DIV:2|cnt0 (|DIV:2|:6)
(16) 27 B TFFE + t 0 0 0 1 4 7 0 |SINE_32:22|cnt4 (|SINE_32:22|:13)
- 23 B DFFE + t 0 0 0 1 3 9 2 |SINE_32:22|cnt2 (|SINE_32:22|:15)
- 26 B DFFE + t 0 0 0 1 2 9 3 |SINE_32:22|cnt1 (|SINE_32:22|:16)
(18) 24 B TFFE + t 0 0 0 1 0 9 3 |SINE_32:22|cnt0 (|SINE_32:22|:17)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC30 |DIV:2|cnt0
| +------------- LC21 laser_pulse_ttl
| | +----------- LC17 q00
| | | +--------- LC19 q_3
| | | | +------- LC27 |SINE_32:22|cnt4
| | | | | +----- LC23 |SINE_32:22|cnt2
| | | | | | +--- LC26 |SINE_32:22|cnt1
| | | | | | | +- LC24 |SINE_32:22|cnt0
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'B'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC17 -> - - * - - - - - | - * - - - - - - | <-- q00
LC19 -> - - - * * - - - | - * - - - - * * | <-- q_3
LC23 -> - - - * * * - - | - * - - - - * * | <-- |SINE_32:22|cnt2
LC26 -> - - - * * * * - | - * - - - - * * | <-- |SINE_32:22|cnt1
LC24 -> - - - * * * * * | - * - - - - * * | <-- |SINE_32:22|cnt0
Pin
17 -> - - * - - - - - | - * * * - - - - | <-- adress_0
18 -> - - * - - - - - | - * * * - - - - | <-- adress_1
84 -> - - - - - - - - | - - - - - - - * | <-- coder_z_ttl
15 -> - * - - - - - - | - * - - - - - - | <-- laser_pulse_lvds
9 -> - - * - - - - - | - * - * - - - - | <-- pdata0
2 -> - - - - - - - - | - - - - - - - * | <-- pulse_ttl
83 -> - - - - - - - - | - - - - - - - - | <-- sine_clk
1 -> - - - * * * * * | - * - - - - - - | <-- sine_rst
16 -> - - * - - - - - | - * * * - - - - | <-- wrrd
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------- LC46 q01
| +----------- LC45 q02
| | +--------- LC43 q03
| | | +------- LC40 q04
| | | | +----- LC38 q05
| | | | | +--- LC37 q06
| | | | | | +- LC35 q07
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'C'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC46 -> * - - - - - - | - - * - - - - - | <-- q01
LC45 -> - * - - - - - | - - * - - - - - | <-- q02
LC43 -> - - * - - - - | - - * - - - - - | <-- q03
LC40 -> - - - * - - - | - - * - - - - - | <-- q04
LC38 -> - - - - * - - | - - * - - - - - | <-- q05
LC37 -> - - - - - * - | - - * - - - - - | <-- q06
LC35 -> - - - - - - * | - - * - - - - - | <-- q07
Pin
17 -> * * * * * * * | - * * * - - - - | <-- adress_0
18 -> * * * * * * * | - * * * - - - - | <-- adress_1
84 -> - - - - - - - | - - - - - - - * | <-- coder_z_ttl
10 -> * - - - - - - | - - * * - - - - | <-- pdata1
11 -> - * - - - - - | - - * * - - - - | <-- pdata2
12 -> - - * - - - - | - - * * - - - - | <-- pdata3
4 -> - - - * - - - | - - * * - - - - | <-- pdata4
5 -> - - - - * - - | - - * * - - - - | <-- pdata5
6 -> - - - - - * - | - - * * - - - - | <-- pdata6
8 -> - - - - - - * | - - * * - - - - | <-- pdata7
2 -> - - - - - - - | - - - - - - - * | <-- pulse_ttl
83 -> - - - - - - - | - - - - - - - - | <-- sine_clk
1 -> - - - - - - - | - * - - - - - - | <-- sine_rst
16 -> * * * * * * * | - * * * - - - - | <-- wrrd
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------- LC64 q10
| +------------- LC61 q11
| | +----------- LC59 q12
| | | +--------- LC57 q13
| | | | +------- LC56 q14
| | | | | +----- LC53 q15
| | | | | | +--- LC51 q16
| | | | | | | +- LC49 q17
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'D'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC64 -> * - - - - - - - | - - - * - - - - | <-- q10
LC61 -> - * - - - - - - | - - - * - - - - | <-- q11
LC59 -> - - * - - - - - | - - - * - - - - | <-- q12
LC57 -> - - - * - - - - | - - - * - - - - | <-- q13
LC56 -> - - - - * - - - | - - - * - - - - | <-- q14
LC53 -> - - - - - * - - | - - - * - - - - | <-- q15
LC51 -> - - - - - - * - | - - - * - - - - | <-- q16
LC49 -> - - - - - - - * | - - - * - - - - | <-- q17
Pin
17 -> * * * * * * * * | - * * * - - - - | <-- adress_0
18 -> * * * * * * * * | - * * * - - - - | <-- adress_1
84 -> - - - - - - - - | - - - - - - - * | <-- coder_z_ttl
9 -> * - - - - - - - | - * - * - - - - | <-- pdata0
10 -> - * - - - - - - | - - * * - - - - | <-- pdata1
11 -> - - * - - - - - | - - * * - - - - | <-- pdata2
12 -> - - - * - - - - | - - * * - - - - | <-- pdata3
4 -> - - - - * - - - | - - * * - - - - | <-- pdata4
5 -> - - - - - * - - | - - * * - - - - | <-- pdata5
6 -> - - - - - - * - | - - * * - - - - | <-- pdata6
8 -> - - - - - - - * | - - * * - - - - | <-- pdata7
2 -> - - - - - - - - | - - - - - - - * | <-- pulse_ttl
83 -> - - - - - - - - | - - - - - - - - | <-- sine_clk
1 -> - - - - - - - - | - * - - - - - - | <-- sine_rst
16 -> * * * * * * * * | - * * * - - - - | <-- wrrd
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC99 data_out0
| +--------- LC101 data_out1
| | +------- LC104 data_out2
| | | +----- LC105 data_out3
| | | | +--- LC107 data_out4
| | | | | +- LC109 data_out5
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
84 -> - - - - - - | - - - - - - - * | <-- coder_z_ttl
2 -> - - - - - - | - - - - - - - * | <-- pulse_ttl
83 -> - - - - - - | - - - - - - - - | <-- sine_clk
1 -> - - - - - - | - * - - - - - - | <-- sine_rst
LC19 -> * * * * * * | - * - - - - * * | <-- q_3
LC27 -> - * * * * * | - - - - - - * * | <-- |SINE_32:22|cnt4
LC23 -> * * * * * * | - * - - - - * * | <-- |SINE_32:22|cnt2
LC26 -> * * * * * * | - * - - - - * * | <-- |SINE_32:22|cnt1
LC24 -> * * * * * * | - * - - - - * * | <-- |SINE_32:22|cnt0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------- LC120 coder_pulse_lvds
| +------------- LC118 coder_z_lvds
| | +----------- LC123 compare_out
| | | +--------- LC115 data_out6
| | | | +------- LC117 data_out7
| | | | | +----- LC122 |DIV:2|cnt2
| | | | | | +--- LC113 |DIV:2|cnt1
| | | | | | | +- LC128 signal_out
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'H'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC122-> - - * - - * - - | - - - - - - - * | <-- |DIV:2|cnt2
LC113-> - - * - - * * - | - - - - - - - * | <-- |DIV:2|cnt1
Pin
80 -> - - - - - - - * | - - - - - - - * | <-- coder_a
79 -> - - - - - - - * | - - - - - - - * | <-- coder_b
84 -> - * - - - - - - | - - - - - - - * | <-- coder_z_ttl
2 -> * - - - - - - - | - - - - - - - * | <-- pulse_ttl
83 -> - - - - - - - - | - - - - - - - - | <-- sine_clk
1 -> - - - - - - - - | - * - - - - - - | <-- sine_rst
LC30 -> - - * - - * * - | - - - - - - - * | <-- |DIV:2|cnt0
LC19 -> - - - * * - - - | - * - - - - * * | <-- q_3
LC27 -> - - - * * - - - | - - - - - - * * | <-- |SINE_32:22|cnt4
LC23 -> - - - * * - - - | - * - - - - * * | <-- |SINE_32:22|cnt2
LC26 -> - - - * * - - - | - * - - - - * * | <-- |SINE_32:22|cnt1
LC24 -> - - - * * - - - | - * - - - - * * | <-- |SINE_32:22|cnt0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** EQUATIONS **
adress_0 : INPUT;
adress_1 : INPUT;
coder_a : INPUT;
coder_b : INPUT;
coder_z_ttl : INPUT;
laser_pulse_lvds : INPUT;
pdata0 : INPUT;
pdata1 : INPUT;
pdata2 : INPUT;
pdata3 : INPUT;
pdata4 : INPUT;
pdata5 : INPUT;
pdata6 : INPUT;
pdata7 : INPUT;
pulse_ttl : INPUT;
sine_clk : INPUT;
sine_rst : INPUT;
wrrd : INPUT;
-- Node name is 'coder_pulse_lvds' = ':8'
-- Equation name is 'coder_pulse_lvds', type is output
coder_pulse_lvds = LCELL( pulse_ttl $ GND);
-- Node name is 'coder_z_lvds' = ':7'
-- Equation name is 'coder_z_lvds', type is output
coder_z_lvds = LCELL( coder_z_ttl $ GND);
-- Node name is 'compare_out' = '|DIV:2|compare_temp'
-- Equation name is 'compare_out', type is output
compare_out = TFFE(!_EQ001, GLOBAL( pulse_ttl), VCC, VCC, VCC);
_EQ001 = _LC122
# _LC113
# _LC030;
-- Node name is 'data_out0' = '|SINE_32:22|:2323'
-- Equation name is 'data_out0', type is output
data_out0 = LCELL( _EQ002 $ GND);
_EQ002 = !_LC024 & !_LC026 & !q_3
# _LC023 & !_LC026
# !_LC023 & _LC024 & _LC026;
-- Node name is 'data_out1' = '|SINE_32:22|:2227'
-- Equation name is 'data_out1', type is output
data_out1 = LCELL( _EQ003 $ GND);
_EQ003 = !_LC023 & _LC024 & !_LC026 & _LC027
# _LC023 & _LC026 & _LC027
# !_LC024 & _LC026 & _LC027
# !_LC023 & !_LC024 & !_LC026 & !_LC027
# !_LC023 & !_LC026 & _LC027 & !q_3;
-- Node name is 'data_out2' = '|SINE_32:22|:2131'
-- Equation name is 'data_out2', type is output
data_out2 = LCELL( _EQ004 $ _EQ005);
_EQ004 = _LC023 & !_LC024 & !_LC026 & !_LC027 & _X001 & _X002 & _X003
# !_LC023 & !_LC024 & _LC026 & !_LC027 & !q_3 & _X001 & _X002 &
_X003
# _LC026 & !_LC027 & q_3 & _X001 & _X002 & _X003 & _X004
# _LC026 & _LC027 & !q_3 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP( _LC024 & !_LC026 & _LC027 & q_3);
_X002 = EXP(!_LC023 & !_LC024 & _LC027 & q_3);
_X003 = EXP( _LC024 & !_LC026 & !_LC027 & !q_3);
_X004 = EXP(!_LC023 & !_LC024);
_EQ005 = _X001 & _X002 & _X003;
_X001 = EXP( _LC024 & !_LC026 & _LC027 & q_3);
_X002 = EXP(!_LC023 & !_LC024 & _LC027 & q_3);
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