📄 composite.rpt
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Project Information d:\laserinterface\cpld\composite.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/26/2006 11:47:24
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
composite
EPM7128SLC84-15 18 30 0 37 4 28 %
User Pins: 18 30 0
Project Information d:\laserinterface\cpld\composite.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'pulse_ttl' chosen for auto global Clock
INFO: Signal 'sine_clk' chosen for auto global Clock
Project Information d:\laserinterface\cpld\composite.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
composite@17 adress_0
composite@18 adress_1
composite@80 coder_a
composite@79 coder_b
composite@76 coder_pulse_lvds
composite@75 coder_z_lvds
composite@84 coder_z_ttl
composite@77 compare_out
composite@64 data_out0
composite@65 data_out1
composite@67 data_out2
composite@68 data_out3
composite@69 data_out4
composite@70 data_out5
composite@73 data_out6
composite@74 data_out7
composite@15 laser_pulse_lvds
composite@20 laser_pulse_ttl
composite@9 pdata0
composite@10 pdata1
composite@11 pdata2
composite@12 pdata3
composite@4 pdata4
composite@5 pdata5
composite@6 pdata6
composite@8 pdata7
composite@2 pulse_ttl
composite@22 q00
composite@24 q01
composite@25 q02
composite@27 q03
composite@21 q_3
composite@28 q04
composite@29 q05
composite@30 q06
composite@31 q07
composite@33 q10
composite@34 q11
composite@35 q12
composite@36 q13
composite@37 q14
composite@39 q15
composite@40 q16
composite@41 q17
composite@81 signal_out
composite@83 sine_clk
composite@1 sine_rst
composite@16 wrrd
Project Information d:\laserinterface\cpld\composite.rpt
** FILE HIERARCHY **
|decoder_latch:1|
|decoder_latch:1|74373:49|
|decoder_latch:1|74373:53|
|decoder_latch:1|74238:56|
|div:2|
|div:2|lpm_add_sub:50|
|div:2|lpm_add_sub:50|addcore:adder|
|div:2|lpm_add_sub:50|addcore:adder|addcore:adder0|
|div:2|lpm_add_sub:50|altshift:result_ext_latency_ffs|
|div:2|lpm_add_sub:50|altshift:carry_ext_latency_ffs|
|div:2|lpm_add_sub:50|altshift:oflow_ext_latency_ffs|
|sine_32:22|
|sine_32:22|lpm_add_sub:107|
|sine_32:22|lpm_add_sub:107|addcore:adder|
|sine_32:22|lpm_add_sub:107|addcore:adder|addcore:adder0|
|sine_32:22|lpm_add_sub:107|altshift:result_ext_latency_ffs|
|sine_32:22|lpm_add_sub:107|altshift:carry_ext_latency_ffs|
|sine_32:22|lpm_add_sub:107|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
***** Logic for device 'composite' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
c
o
d
e
r c
c c _ o
o s o p d
p d i m u e
u s e s g p l r
l i r i n c c a s _
p p p p p p p V s n _ n a o o r e z
d d d d d d d C e e z e l d d V e _ _
a a a a a a a C _ _ _ _ _ e e C _ l l
t t t t G t t t I t r t c G o r r C o v v
a a a a N a a a N t s t l N u _ _ I u d d
2 1 0 7 D 6 5 4 T l t l k D t a b O t s s
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
pdata3 | 12 74 | data_out7
VCCIO | 13 73 | data_out6
#TDI | 14 72 | GND
laser_pulse_lvds | 15 71 | #TDO
wrrd | 16 70 | data_out5
adress_0 | 17 69 | data_out4
adress_1 | 18 68 | data_out3
GND | 19 67 | data_out2
laser_pulse_ttl | 20 66 | VCCIO
q_3 | 21 65 | data_out1
q00 | 22 EPM7128SLC84-15 64 | data_out0
#TMS | 23 63 | RESERVED
q01 | 24 62 | #TCK
q02 | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
q03 | 27 59 | GND
q04 | 28 58 | RESERVED
q05 | 29 57 | RESERVED
q06 | 30 56 | RESERVED
q07 | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
q q q q q V q q q G V R R R G R R R R R V
1 1 1 1 1 C 1 1 1 N C E E E N E E E E E C
0 1 2 3 4 C 5 6 7 D C S S S D S S S S S C
I I E E E E E E E E I
O N R R R R R R R R O
T V V V V V V V V
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 8/ 8(100%) 2/16( 12%) 11/36( 30%)
C: LC33 - LC48 7/16( 43%) 8/ 8(100%) 7/16( 43%) 17/36( 47%)
D: LC49 - LC64 8/16( 50%) 8/ 8(100%) 8/16( 50%) 19/36( 52%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 6/16( 37%) 7/ 8( 87%) 8/16( 50%) 5/36( 13%)
H: LC113 - LC128 8/16( 50%) 8/ 8(100%) 1/16( 6%) 12/36( 33%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 48/64 ( 75%)
Total logic cells used: 37/128 ( 28%)
Total shareable expanders used: 4/128 ( 3%)
Total Turbo logic cells used: 37/128 ( 28%)
Total shareable expanders not available (n/a): 22/128 ( 17%)
Average fan-in: 4.40
Total fan-in: 163
Total input pins required: 18
Total fast input logic cells required: 0
Total output pins required: 30
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 37
Total flipflops required: 9
Total product terms required: 150
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
17 (25) (B) INPUT 0 0 0 0 0 16 0 adress_0
18 (24) (B) INPUT 0 0 0 0 0 16 0 adress_1
80 (126) (H) INPUT 0 0 0 0 0 1 0 coder_a
79 (125) (H) INPUT 0 0 0 0 0 1 0 coder_b
84 - - INPUT 0 0 0 0 0 1 0 coder_z_ttl
15 (29) (B) INPUT 0 0 0 0 0 1 0 laser_pulse_lvds
9 (8) (A) INPUT 0 0 0 0 0 2 0 pdata0
10 (6) (A) INPUT 0 0 0 0 0 2 0 pdata1
11 (5) (A) INPUT 0 0 0 0 0 2 0 pdata2
12 (3) (A) INPUT 0 0 0 0 0 2 0 pdata3
4 (16) (A) INPUT 0 0 0 0 0 2 0 pdata4
5 (14) (A) INPUT 0 0 0 0 0 2 0 pdata5
6 (13) (A) INPUT 0 0 0 0 0 2 0 pdata6
8 (11) (A) INPUT 0 0 0 0 0 2 0 pdata7
2 - - INPUT G 0 0 0 0 0 1 0 pulse_ttl
83 - - INPUT G 0 0 0 0 0 0 0 sine_clk
1 - - INPUT 0 0 0 0 0 1 4 sine_rst
16 (27) (B) INPUT 0 0 0 0 0 16 0 wrrd
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\laserinterface\cpld\composite.rpt
composite
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
76 120 H OUTPUT t 0 0 0 1 0 0 0 coder_pulse_lvds
75 118 H OUTPUT t 0 0 0 1 0 0 0 coder_z_lvds
77 123 H FF + t 0 0 0 0 3 0 0 compare_out (|DIV:2|:7)
64 99 G OUTPUT t 0 0 0 0 4 0 0 data_out0
65 101 G OUTPUT t 1 0 1 0 5 0 0 data_out1
67 104 G OUTPUT t 5 0 1 0 5 0 0 data_out2
68 105 G OUTPUT t 1 0 1 0 5 0 0 data_out3
69 107 G OUTPUT t 0 0 0 0 5 0 0 data_out4
70 109 G OUTPUT t 1 0 1 0 5 0 0 data_out5
73 115 H OUTPUT t 1 0 1 0 5 0 0 data_out6
74 117 H OUTPUT t 0 0 0 0 5 0 0 data_out7
20 21 B OUTPUT t 0 0 0 1 0 0 0 laser_pulse_ttl
22 17 B OUTPUT t 1 0 1 4 1 1 0 q00
24 46 C OUTPUT t 1 0 1 4 1 1 0 q01
25 45 C OUTPUT t 1 0 1 4 1 1 0 q02
27 43 C OUTPUT t 1 0 1 4 1 1 0 q03
21 19 B FF + t 1 0 1 1 4 9 1 q_3 (|SINE_32:22|:14)
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