📄 sam7s.h
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#define SSC_RC0R (*AT91C_SSC_RC0R) // (SSC) Receive Compare 0 Register
#define SSC_RSHR (*AT91C_SSC_RSHR) // (SSC) Receive Sync Holding Register
#define SSC_RHR (*AT91C_SSC_RHR) // (SSC) Receive Holding Register
#define SSC_TCMR (*AT91C_SSC_TCMR) // (SSC) Transmit Clock Mode Register
#define SSC_RCMR (*AT91C_SSC_RCMR) // (SSC) Receive Clock ModeRegister
#define SSC_CR (*AT91C_SSC_CR) // (SSC) Control Register
#define SSC_IMR (*AT91C_SSC_IMR) // (SSC) Interrupt Mask Register
#define SSC_IER (*AT91C_SSC_IER) // (SSC) Interrupt Enable Register
#define SSC_RC1R (*AT91C_SSC_RC1R) // (SSC) Receive Compare 1 Register
#define SSC_TSHR (*AT91C_SSC_TSHR) // (SSC) Transmit Sync Holding Register
#define SSC_THR (*AT91C_SSC_THR) // (SSC) Transmit Holding Register
#define SSC_TFMR (*AT91C_SSC_TFMR) // (SSC) Transmit Frame Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define US1_PTSR (*AT91C_US1_PTSR) // (PDC_US1) PDC Transfer Status Register
#define US1_TNCR (*AT91C_US1_TNCR) // (PDC_US1) Transmit Next Counter Register
#define US1_RNCR (*AT91C_US1_RNCR) // (PDC_US1) Receive Next Counter Register
#define US1_TCR (*AT91C_US1_TCR) // (PDC_US1) Transmit Counter Register
#define US1_RCR (*AT91C_US1_RCR) // (PDC_US1) Receive Counter Register
#define US1_PTCR (*AT91C_US1_PTCR) // (PDC_US1) PDC Transfer Control Register
#define US1_TNPR (*AT91C_US1_TNPR) // (PDC_US1) Transmit Next Pointer Register
#define US1_RNPR (*AT91C_US1_RNPR) // (PDC_US1) Receive Next Pointer Register
#define US1_TPR (*AT91C_US1_TPR) // (PDC_US1) Transmit Pointer Register
#define US1_RPR (*AT91C_US1_RPR) // (PDC_US1) Receive Pointer Register
// ========== Register definition for US1 peripheral ==========
#define US1_XXR (*AT91C_US1_XXR) // (US1) XON_XOFF Register
#define US1_RHR (*AT91C_US1_RHR) // (US1) Receiver Holding Register
#define US1_IMR (*AT91C_US1_IMR) // (US1) Interrupt Mask Register
#define US1_IER (*AT91C_US1_IER) // (US1) Interrupt Enable Register
#define US1_CR (*AT91C_US1_CR) // (US1) Control Register
#define US1_RTOR (*AT91C_US1_RTOR) // (US1) Receiver Time-out Register
#define US1_THR (*AT91C_US1_THR) // (US1) Transmitter Holding Register
#define US1_CSR (*AT91C_US1_CSR) // (US1) Channel Status Register
#define US1_IDR (*AT91C_US1_IDR) // (US1) Interrupt Disable Register
#define US1_FIDI (*AT91C_US1_FIDI) // (US1) FI_DI_Ratio Register
#define US1_BRGR (*AT91C_US1_BRGR) // (US1) Baud Rate Generator Register
#define US1_TTGR (*AT91C_US1_TTGR) // (US1) Transmitter Time-guard Register
#define US1_IF (*AT91C_US1_IF) // (US1) IRDA_FILTER Register
#define US1_NER (*AT91C_US1_NER) // (US1) Nb Errors Register
#define US1_MR (*AT91C_US1_MR) // (US1) Mode Register
// ========== Register definition for PDC_US0 peripheral ==========
#define US0_PTCR (*AT91C_US0_PTCR) // (PDC_US0) PDC Transfer Control Register
#define US0_TNPR (*AT91C_US0_TNPR) // (PDC_US0) Transmit Next Pointer Register
#define US0_RNPR (*AT91C_US0_RNPR) // (PDC_US0) Receive Next Pointer Register
#define US0_TPR (*AT91C_US0_TPR) // (PDC_US0) Transmit Pointer Register
#define US0_RPR (*AT91C_US0_RPR) // (PDC_US0) Receive Pointer Register
#define US0_PTSR (*AT91C_US0_PTSR) // (PDC_US0) PDC Transfer Status Register
#define US0_TNCR (*AT91C_US0_TNCR) // (PDC_US0) Transmit Next Counter Register
#define US0_RNCR (*AT91C_US0_RNCR) // (PDC_US0) Receive Next Counter Register
#define US0_TCR (*AT91C_US0_TCR) // (PDC_US0) Transmit Counter Register
#define US0_RCR (*AT91C_US0_RCR) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define US0_TTGR (*AT91C_US0_TTGR) // (US0) Transmitter Time-guard Register
#define US0_BRGR (*AT91C_US0_BRGR) // (US0) Baud Rate Generator Register
#define US0_RHR (*AT91C_US0_RHR) // (US0) Receiver Holding Register
#define US0_IMR (*AT91C_US0_IMR) // (US0) Interrupt Mask Register
#define US0_NER (*AT91C_US0_NER) // (US0) Nb Errors Register
#define US0_RTOR (*AT91C_US0_RTOR) // (US0) Receiver Time-out Register
#define US0_XXR (*AT91C_US0_XXR) // (US0) XON_XOFF Register
#define US0_FIDI (*AT91C_US0_FIDI) // (US0) FI_DI_Ratio Register
#define US0_CR (*AT91C_US0_CR) // (US0) Control Register
#define US0_IER (*AT91C_US0_IER) // (US0) Interrupt Enable Register
#define US0_IF (*AT91C_US0_IF) // (US0) IRDA_FILTER Register
#define US0_MR (*AT91C_US0_MR) // (US0) Mode Register
#define US0_IDR (*AT91C_US0_IDR) // (US0) Interrupt Disable Register
#define US0_CSR (*AT91C_US0_CSR) // (US0) Channel Status Register
#define US0_THR (*AT91C_US0_THR) // (US0) Transmitter Holding Register
// ========== Register definition for TWI peripheral ==========
#define TWI_RHR (*AT91C_TWI_RHR) // (TWI) Receive Holding Register
#define TWI_IDR (*AT91C_TWI_IDR) // (TWI) Interrupt Disable Register
#define TWI_SR (*AT91C_TWI_SR) // (TWI) Status Register
#define TWI_CWGR (*AT91C_TWI_CWGR) // (TWI) Clock Waveform Generator Register
#define TWI_SMR (*AT91C_TWI_SMR) // (TWI) Slave Mode Register
#define TWI_CR (*AT91C_TWI_CR) // (TWI) Control Register
#define TWI_THR (*AT91C_TWI_THR) // (TWI) Transmit Holding Register
#define TWI_IMR (*AT91C_TWI_IMR) // (TWI) Interrupt Mask Register
#define TWI_IER (*AT91C_TWI_IER) // (TWI) Interrupt Enable Register
#define TWI_IADR (*AT91C_TWI_IADR) // (TWI) Internal Address Register
#define TWI_MMR (*AT91C_TWI_MMR) // (TWI) Master Mode Register
// ========== Register definition for TC2 peripheral ==========
#define TC2_IMR (*AT91C_TC2_IMR) // (TC2) Interrupt Mask Register
#define TC2_IER (*AT91C_TC2_IER) // (TC2) Interrupt Enable Register
#define TC2_RC (*AT91C_TC2_RC) // (TC2) Register C
#define TC2_RA (*AT91C_TC2_RA) // (TC2) Register A
#define TC2_CMR (*AT91C_TC2_CMR) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC2_IDR (*AT91C_TC2_IDR) // (TC2) Interrupt Disable Register
#define TC2_SR (*AT91C_TC2_SR) // (TC2) Status Register
#define TC2_RB (*AT91C_TC2_RB) // (TC2) Register B
#define TC2_CV (*AT91C_TC2_CV) // (TC2) Counter Value
#define TC2_CCR (*AT91C_TC2_CCR) // (TC2) Channel Control Register
// ========== Register definition for TC1 peripheral ==========
#define TC1_IMR (*AT91C_TC1_IMR) // (TC1) Interrupt Mask Register
#define TC1_IER (*AT91C_TC1_IER) // (TC1) Interrupt Enable Register
#define TC1_RC (*AT91C_TC1_RC) // (TC1) Register C
#define TC1_RA (*AT91C_TC1_RA) // (TC1) Register A
#define TC1_CMR (*AT91C_TC1_CMR) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC1_IDR (*AT91C_TC1_IDR) // (TC1) Interrupt Disable Register
#define TC1_SR (*AT91C_TC1_SR) // (TC1) Status Register
#define TC1_RB (*AT91C_TC1_RB) // (TC1) Register B
#define TC1_CV (*AT91C_TC1_CV) // (TC1) Counter Value
#define TC1_CCR (*AT91C_TC1_CCR) // (TC1) Channel Control Register
// ========== Register definition for TC0 peripheral ==========
#define TC0_IMR (*AT91C_TC0_IMR) // (TC0) Interrupt Mask Register
#define TC0_IER (*AT91C_TC0_IER) // (TC0) Interrupt Enable Register
#define TC0_RC (*AT91C_TC0_RC) // (TC0) Register C
#define TC0_RA (*AT91C_TC0_RA) // (TC0) Register A
#define TC0_CMR (*AT91C_TC0_CMR) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
#define TC0_IDR (*AT91C_TC0_IDR) // (TC0) Interrupt Disable Register
#define TC0_SR (*AT91C_TC0_SR) // (TC0) Status Register
#define TC0_RB (*AT91C_TC0_RB) // (TC0) Register B
#define TC0_CV (*AT91C_TC0_CV) // (TC0) Counter Value
#define TC0_CCR (*AT91C_TC0_CCR) // (TC0) Channel Control Register
// ========== Register definition for TCB peripheral ==========
#define TCB_BMR (*AT91C_TCB_BMR) // (TCB) TC Block Mode Register
#define TCB_BCR (*AT91C_TCB_BCR) // (TCB) TC Block Control Register
// ========== Register definition for PWMC_CH3 peripheral ==========
#define CH3_CUPDR (*AT91C_CH3_CUPDR) // (PWMC_CH3) Channel Update Register
#define CH3_CPRDR (*AT91C_CH3_CPRDR) // (PWMC_CH3) Channel Period Register
#define CH3_CMR (*AT91C_CH3_CMR) // (PWMC_CH3) Channel Mode Register
#define CH3_Reserved (*AT91C_CH3_Reserved) // (PWMC_CH3) Reserved
#define CH3_CCNTR (*AT91C_CH3_CCNTR) // (PWMC_CH3) Channel Counter Register
#define CH3_CDTYR (*AT91C_CH3_CDTYR) // (PWMC_CH3) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH2 peripheral ==========
#define CH2_CUPDR (*AT91C_CH2_CUPDR) // (PWMC_CH2) Channel Update Register
#define CH2_CPRDR (*AT91C_CH2_CPRDR) // (PWMC_CH2) Channel Period Register
#define CH2_CMR (*AT91C_CH2_CMR) // (PWMC_CH2) Channel Mode Register
#define CH2_Reserved (*AT91C_CH2_Reserved) // (PWMC_CH2) Reserved
#define CH2_CCNTR (*AT91C_CH2_CCNTR) // (PWMC_CH2) Channel Counter Register
#define CH2_CDTYR (*AT91C_CH2_CDTYR) // (PWMC_CH2) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH1 peripheral ==========
#define CH1_CUPDR (*AT91C_CH1_CUPDR) // (PWMC_CH1) Channel Update Register
#define CH1_CPRDR (*AT91C_CH1_CPRDR) // (PWMC_CH1) Channel Period Register
#define CH1_CMR (*AT91C_CH1_CMR) // (PWMC_CH1) Channel Mode Register
#define CH1_Reserved (*AT91C_CH1_Reserved) // (PWMC_CH1) Reserved
#define CH1_CCNTR (*AT91C_CH1_CCNTR) // (PWMC_CH1) Channel Counter Register
#define CH1_CDTYR (*AT91C_CH1_CDTYR) // (PWMC_CH1) Channel Duty Cycle Register
// ========== Register definition for PWMC_CH0 peripheral ==========
#define CH0_CUPDR (*AT91C_CH0_CUPDR) // (PWMC_CH0) Channel Update Register
#define CH0_CPRDR (*AT91C_CH0_CPRDR) // (PWMC_CH0) Channel Period Register
#define CH0_CMR (*AT91C_CH0_CMR) // (PWMC_CH0) Channel Mode Register
#define CH0_Reserved (*AT91C_CH0_Reserved) // (PWMC_CH0) Reserved
#define CH0_CCNTR (*AT91C_CH0_CCNTR) // (PWMC_CH0) Channel Counter Register
#define CH0_CDTYR (*AT91C_CH0_CDTYR) // (PWMC_CH0) Channel Duty Cycle Register
// ========== Register definition for PWMC peripheral ==========
#define PWMC_VR (*AT91C_PWMC_VR) // (PWMC) PWMC Version Register
#define PWMC_ISR (*AT91C_PWMC_ISR) // (PWMC) PWMC Interrupt Status Register
#define PWMC_IDR (*AT91C_PWMC_IDR) // (PWMC) PWMC Interrupt Disable Register
#define PWMC_SR (*AT91C_PWMC_SR) // (PWMC) PWMC Status Register
#define PWMC_ENA (*AT91C_PWMC_ENA) // (PWMC) PWMC Enable Register
#define PWMC_IMR (*AT91C_PWMC_IMR) // (PWMC) PWMC Interrupt Mask Register
#define PWMC_MR (*AT91C_PWMC_MR) // (PWMC) PWMC Mode Register
#define PWMC_DIS (*AT91C_PWMC_DIS) // (PWMC) PWMC Disable Register
#define PWMC_IER (*AT91C_PWMC_IER) // (PWMC) PWMC Interrupt Enable Register
// ========== Register definition for UDP peripheral ==========
#define UDP_ISR (*AT91C_UDP_ISR) // (UDP) Interrupt Status Register
#define UDP_IDR (*AT91C_UDP_IDR) // (UDP) Interrupt Disable Register
#define UDP_GLBSTATE (*AT91C_UDP_GLBSTATE) // (UDP) Global State Register
#define UDP_FDR (*AT91C_UDP_FDR) // (UDP) Endpoint FIFO Data Register
#define UDP_CSR (*AT91C_UDP_CSR) // (UDP) Endpoint Control and Status Register
#define UDP_RSTEP (*AT91C_UDP_RSTEP) // (UDP) Reset Endpoint Register
#define UDP_ICR (*AT91C_UDP_ICR) // (UDP) Interrupt Clear Register
#define UDP_IMR (*AT91C_UDP_IMR) // (UDP) Interrupt Mask Register
#define UDP_IER (*AT91C_UDP_IER) // (UDP) Interrupt Enable Register
#define UDP_FADDR (*AT91C_UDP_FADDR) // (UDP) Function Address Register
#define UDP_NUM (*AT91C_UDP_NUM) // (UDP) Frame Number Register
/* Port Pins */
#define PA0 (1<<0)
#define PA1 (1<<1)
#define PA2 (1<<2)
#define PA3 (1<<3)
#define PA4 (1<<4)
#define PA5 (1<<5)
#define PA6 (1<<6)
#define PA7 (1<<7)
#define PA8 (1<<8)
#define PA9 (1<<9)
#define PA10 (1<<10)
#define PA11 (1<<11)
#define PA12 (1<<12)
#define PA13 (1<<13)
#define PA14 (1<<14)
#define PA15 (1<<15)
#define PA16 (1<<16)
#define PA17 (1<<17)
#define PA18 (1<<18)
#define PA19 (1<<19)
#define PA20 (1<<20)
#define PA21 (1<<21)
#define PA22 (1<<22)
#define PA23 (1<<23)
#define PA24 (1<<24)
#define PA25 (1<<25)
#define PA26 (1<<26)
#define PA27 (1<<27)
#define PA28 (1<<28)
#define PA29 (1<<29)
#define PA30 (1<<30)
#define PA31 (1<<31)
#endif
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