📄 sam7s.h
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/*-----------------------------------------------------------------------------
ARM菜鸟改造令人烦恼的头文件AT91SAM7S64.H
改造原因: 令人烦恼的*AT91C_,使书写更加符合日常习惯.结构及结构指针的写法很烦人.
虽然可能优化代码,但本头文件效率相同.
其他AT91下列有PIO.H等头文件,但对AT91SAM7S64不太适合
文件名: AT91SAM7S64DEF.H
HotPower@126.com 2005.8.24 于西安大雁塔村队部 (首次修改)
-------------------------------------------------------------------------------*/
#include <AT91SAM7S64.H>
#ifndef AT91SAM7S64DEF_H
#define AT91SAM7S64DEF_H
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
// *****************************************************************************
// ========== Register definition for SYSC peripheral ==========
#define SYSC_VRPM (*AT91C_SYSC_SYSC_VRPM) // (SYSC) Voltage Regulator Power Mode Register
// ========== Register definition for AIC peripheral ==========
#define AIC_ICCR (*AT91C_AIC_ICCR) // (AIC) Interrupt Clear Command Register
#define AIC_IECR (*AT91C_AIC_IECR) // (AIC) Interrupt Enable Command Register
#define AIC_SMR (*AT91C_AIC_SMR) // (AIC) Source Mode Register
#define AIC_ISCR (*AT91C_AIC_ISCR) // (AIC) Interrupt Set Command Register
#define AIC_EOICR (*AT91C_AIC_EOICR) // (AIC) End of Interrupt Command Register
#define AIC_DCR (*AT91C_AIC_DCR) // (AIC) Debug Control Register (Protect)
#define AIC_FFER (*AT91C_AIC_FFER) // (AIC) Fast Forcing Enable Register
#define AIC_SVR (*AT91C_AIC_SVR) // (AIC) Source Vector Register
#define AIC_SPU (*AT91C_AIC_SPU) // (AIC) Spurious Vector Register
#define AIC_FFDR (*AT91C_AIC_FFDR) // (AIC) Fast Forcing Disable Register
#define AIC_FVR (*AT91C_AIC_FVR) // (AIC) FIQ Vector Register
#define AIC_FFSR (*AT91C_AIC_FFSR) // (AIC) Fast Forcing Status Register
#define AIC_IMR (*AT91C_AIC_IMR) // (AIC) Interrupt Mask Register
#define AIC_ISR (*AT91C_AIC_ISR) // (AIC) Interrupt Status Register
#define AIC_IVR (*AT91C_AIC_IVR) // (AIC) IRQ Vector Register
#define AIC_IDCR (*AT91C_AIC_IDCR) // (AIC) Interrupt Disable Command Register
#define AIC_CISR (*AT91C_AIC_CISR) // (AIC) Core Interrupt Status Register
#define AIC_IPR (*AT91C_AIC_IPR) // (AIC) Interrupt Pending Register
// ========== Register definition for DBGU peripheral ==========
#define DBGU_C2R (*AT91C_DBGU_C2R) // (DBGU) Chip ID2 Register
#define DBGU_THR (*AT91C_DBGU_THR) // (DBGU) Transmitter Holding Register
#define DBGU_CSR (*AT91C_DBGU_CSR) // (DBGU) Channel Status Register
#define DBGU_CSR (*AT91C_DBGU_CSR) // (DBGU) Interrupt Disable Register
#define DBGU_CSR (*AT91C_DBGU_CSR) // (DBGU) Mode Register
#define DBGU_FNTR (*AT91C_DBGU_FNTR) // (DBGU) Force NTRST Register
#define DBGU_C1R (*AT91C_DBGU_C1R) // (DBGU) Chip ID1 Register
#define DBGU_BRGR (*AT91C_DBGU_BRGR) // (DBGU) Baud Rate Generator Register
#define DBGU_RHR (*AT91C_DBGU_RHR) // (DBGU) Receiver Holding Register
#define DBGU_IMR (*AT91C_DBGU_IMR) // (DBGU) Interrupt Mask Register
#define DBGU_IER (*AT91C_DBGU_IER) // (DBGU) Interrupt Enable Register
#define DBGU_CR (*AT91C_DBGU_CR) // (DBGU) Control Register
// ========== Register definition for PDC_DBGU peripheral ==========
#define DBGU_TNCR (*AT91C_DBGU_TNCR) // (PDC_DBGU) Transmit Next Counter Register
#define DBGU_RNCR (*AT91C_DBGU_RNCR) // (PDC_DBGU) Receive Next Counter Register
#define DBGU_PTCR (*AT91C_DBGU_PTCR) // (PDC_DBGU) PDC Transfer Control Register
#define DBGU_PTSR (*AT91C_DBGU_PTSR) // (PDC_DBGU) PDC Transfer Status Register
#define DBGU_RCR (*AT91C_DBGU_RCR) // (PDC_DBGU) Receive Counter Register
#define DBGU_TCR (*AT91C_DBGU_TCR) // (PDC_DBGU) Transmit Counter Register
#define DBGU_RPR (*AT91C_DBGU_RPR) // (PDC_DBGU) Receive Pointer Register
#define DBGU_RPR (*AT91C_DBGU_RPR) // (PDC_DBGU) Transmit Pointer Register
#define DBGU_RNPR (*AT91C_DBGU_RNPR) // (PDC_DBGU) Receive Next Pointer Register
#define DBGU_TNPR (*AT91C_DBGU_TNPR) // (PDC_DBGU) Transmit Next Pointer Register
// ========== Register definition for PIOA peripheral ==========
#define PIO_IMR (*AT91C_PIOA_IMR) // (PIOA) Interrupt Mask Register
#define PIO_IER (*AT91C_PIOA_IER) // (PIOA) Interrupt Enable Register
#define PIO_OWDR (*AT91C_PIOA_OWDR) // (PIOA) Output Write Disable Register
#define PIO_ISR (*AT91C_PIOA_ISR) // (PIOA) Interrupt Status Register
#define PIO_PPUDR (*AT91C_PIOA_PPUDR) // (PIOA) Pull-up Disable Register
#define PIO_MDSR (*AT91C_PIOA_MDSR) // (PIOA) Multi-driver Status Register
#define PIO_MDER (*AT91C_PIOA_MDER) // (PIOA) Multi-driver Enable Register
#define PIO_PER (*AT91C_PIOA_PER) // (PIOA) PIO Enable Register
#define PIO_PSR (*AT91C_PIOA_PSR) // (PIOA) PIO Status Register
#define PIO_OER (*AT91C_PIOA_OER) // (PIOA) Output Enable Register
#define PIO_BSR (*AT91C_PIOA_BSR) // (PIOA) Select B Register
#define PIO_PPUER (*AT91C_PIOA_PPUER) // (PIOA) Pull-up Enable Register
#define PIO_MDDR (*AT91C_PIOA_MDDR) // (PIOA) Multi-driver Disable Register
#define PIO_PDR (*AT91C_PIOA_PDR) // (PIOA) PIO Disable Register
#define PIO_ODR (*AT91C_PIOA_ODR) // (PIOA) Output Disable Registerr
#define PIO_IFDR (*AT91C_PIOA_IFDR) // (PIOA) Input Filter Disable Register
#define PIO_ABSR (*AT91C_PIOA_ABSR) // (PIOA) AB Select Status Register
#define PIO_ASR (*AT91C_PIOA_ASR) // (PIOA) Select A Register
#define PIO_PPUSR (*AT91C_PIOA_PPUSR8) // (PIOA) Pad Pull-up Status Register
#define PIO_ODSR (*AT91C_PIOA_ODSR) // (PIOA) Output Data Status Register
#define PIO_SODR (*AT91C_PIOA_SODR) // (PIOA) Set Output Data Register
#define PIO_IFSR (*AT91C_PIOA_IFSR) // (PIOA) Input Filter Status Register
#define PIO_IFER (*AT91C_PIOA_IFER) // (PIOA) Input Filter Enable Register
#define PIO_OSR (*AT91C_PIOA_OSR) // (PIOA) Output Status Register
#define PIO_IDR (*AT91C_PIOA_IDR) // (PIOA) Interrupt Disable Register
#define PIO_PDSR (*AT91C_PIOA_PDSR) // (PIOA) Pin Data Status Register
#define PIO_CODR (*AT91C_PIOA_CODR) // (PIOA) Clear Output Data Register
#define PIO_OWSR (*AT91C_PIOA_OWSR) // (PIOA) Output Write Status Register
#define PIO_OWER (*AT91C_PIOA_OWER) // (PIOA) Output Write Enable Register
// ========== Register definition for CKGR peripheral ==========
#define CKGR_PLLR (*AT91C_CKGR_PLLR) // (CKGR) PLL Register
#define CKGR_MCFR (*AT91C_CKGR_MCFR) // (CKGR) Main Clock Frequency Register
#define CKGR_MOR (*AT91C_CKGR_MOR) // (CKGR) Main Oscillator Register
// ========== Register definition for PMC peripheral ==========
#define PMC_SCSR (*AT91C_PMC_SCSR) // (PMC) System Clock Status Register
#define PMC_SCER (*AT91C_PMC_SCER) // (PMC) System Clock Enable Register
#define PMC_IMR (*AT91C_PMC_IMR) // (PMC) Interrupt Mask Register
#define PMC_IDR (*AT91C_PMC_IDR) // (PMC) Interrupt Disable Register
#define PMC_PCDR (*AT91C_PMC_PCDR) // (PMC) Peripheral Clock Disable Register
#define PMC_SCDR (*AT91C_PMC_SCDR) // (PMC) System Clock Disable Register
#define PMC_SR (*AT91C_PMC_SR) // (PMC) Status Register
#define PMC_IER (*AT91C_PMC_IER) // (PMC) Interrupt Enable Register
#define PMC_MCKR (*AT91C_PMC_MCKR) // (PMC) Master Clock Register
#define PMC_MOR (*AT91C_PMC_MOR) // (PMC) Main Oscillator Register
#define PMC_PCER (*AT91C_PMC_PCER) // (PMC) Peripheral Clock Enable Register
#define PMC_PCSR (*AT91C_PMC_PCSR) // (PMC) Peripheral Clock Status Register
#define PMC_PLLR (*AT91C_PMC_PLLR) // (PMC) PLL Register
#define PMC_MCFR (*AT91C_PMC_MCFR) // (PMC) Main Clock Frequency Register
#define PMC_PCKR (*AT91C_PMC_PCKR) // (PMC) Programmable Clock Register
// ========== Register definition for RSTC peripheral ==========
#define RSTC_SR (*AT91C_RSTC_RSR) // (RSTC) Reset Status Register
#define RSTC_MR (*AT91C_RSTC_RMR) // (RSTC) Reset Mode Register
#define RSTC_CR (*AT91C_RSTC_RCR) // (RSTC) Reset Control Register
// ========== Register definition for RTTC peripheral ==========
#define RTT_SR (*AT91C_RTTC_RTSR) // (RTTC) Real-time Status Register
#define RTT_AR (*AT91C_RTTC_RTAR) // (RTTC) Real-time Alarm Register
#define RTT_VR (*AT91C_RTTC_RTVR) // (RTTC) Real-time Value Register
#define RTT_MR (*AT91C_RTTC_RTMR) // (RTTC) Real-time Mode Register
// ========== Register definition for PITC peripheral ==========
#define PIT_PIIR (*AT91C_PITC_PIIR) // (PITC) Period Interval Image Register
#define PIT_SR (*AT91C_PITC_PISR) // (PITC) Period Interval Status Register
#define PIT_PIVR (*AT91C_PITC_PIVR) // (PITC) Period Interval Value Register
#define PIT_MR (*AT91C_PITC_PIMR) // (PITC) Period Interval Mode Register
// ========== Register definition for WDTC peripheral ==========
#define WDT_MR (*AT91C_WDTC_WDMR) // (WDTC) Watchdog Mode Register
#define WDT_SR (*AT91C_WDTC_WDSR) // (WDTC) Watchdog Status Register
#define WDT_CR (*AT91C_WDTC_WDCR) // (WDTC) Watchdog Control Register
// ========== Register definition for MC peripheral ==========
#define MC_FCR (*AT91C_MC_FCR) // (MC) MC Flash Command Register
#define MC_ASR (*AT91C_MC_ASR) // (MC) MC Abort Status Register
#define MC_FSR (*AT91C_MC_FSR) // (MC) MC Flash Status Register
#define MC_FMR (*AT91C_MC_FMR) // (MC) MC Flash Mode Register
#define MC_AASR (*AT91C_MC_AASR) // (MC) MC Abort Address Status Register
#define MC_RCR (*AT91C_MC_RCR) // (MC) MC Remap Control Register
// ========== Register definition for PDC_SPI peripheral ==========
#define SPI_PTCR (*AT91C_SPI_PTCR) // (PDC_SPI) PDC Transfer Control Register
#define SPI_TNPR (*AT91C_SPI_TNPR) // (PDC_SPI) Transmit Next Pointer Register
#define SPI_RNPR (*AT91C_SPI_RNPR) // (PDC_SPI) Receive Next Pointer Register
#define SPI_TPR (*AT91C_SPI_TPR) // (PDC_SPI) Transmit Pointer Register
#define SPI_RPR (*AT91C_SPI_RPR) // (PDC_SPI) Receive Pointer Register
#define SPI_PTSR (*AT91C_SPI_PTSR) // (PDC_SPI) PDC Transfer Status Register
#define SPI_TNCR (*AT91C_SPI_TNCR) // (PDC_SPI) Transmit Next Counter Register
#define SPI_RNCR (*AT91C_SPI_RNCR) // (PDC_SPI) Receive Next Counter Register
#define SPI_TCR (*AT91C_SPI_TCR) // (PDC_SPI) Transmit Counter Register
#define SPI_RCR (*AT91C_SPI_RCR) // (PDC_SPI) Receive Counter Register
// ========== Register definition for SPI peripheral ==========
#define SPI_CSR (*AT91C_SPI_CSR) // (SPI) Chip Select Register
#define SPI_IDR (*AT91C_SPI_IDR) // (SPI) Interrupt Disable Register
#define SPI_SR (*AT91C_SPI_SR) // (SPI) Status Register
#define SPI_RDR (*AT91C_SPI_RDR) // (SPI) Receive Data Register
#define SPI_CR (*AT91C_SPI_CR) // (SPI) Control Register
#define SPI_IMR (*AT91C_SPI_IMR) // (SPI) Interrupt Mask Register
#define SPI_IER (*AT91C_SPI_IER) // (SPI) Interrupt Enable Register
#define SPI_TDR (*AT91C_SPI_TDR) // (SPI) Transmit Data Register
#define SPI_MR (*AT91C_SPI_MR) // (SPI) Mode Register
// ========== Register definition for PDC_ADC peripheral ==========
#define ADC_PTCR (*AT91C_ADC_PTCR) // (PDC_ADC) PDC Transfer Control Register
#define ADC_TNPR (*AT91C_ADC_TNPR) // (PDC_ADC) Transmit Next Pointer Register
#define ADC_RNPR (*AT91C_ADC_RNPR) // (PDC_ADC) Receive Next Pointer Register
#define ADC_TPR (*AT91C_ADC_TPR) // (PDC_ADC) Transmit Pointer Register
#define ADC_RPR (*AT91C_ADC_RPR) // (PDC_ADC) Receive Pointer Register
#define ADC_PTSR (*AT91C_ADC_PTSR) // (PDC_ADC) PDC Transfer Status Register
#define ADC_TNCR (*AT91C_ADC_TNCR) // (PDC_ADC) Transmit Next Counter Register
#define ADC_RNCR (*AT91C_ADC_RNCR) // (PDC_ADC) Receive Next Counter Register
#define ADC_TCR (*AT91C_ADC_TCR) // (PDC_ADC) Transmit Counter Register
#define ADC_RCR (*AT91C_ADC_RCR) // (PDC_ADC) Receive Counter Register
// ========== Register definition for ADC peripheral ==========
#define ADC_IMR (*AT91C_ADC_IMR) // (ADC) ADC Interrupt Mask Register
#define ADC_CDR4 (*AT91C_ADC_CDR4) // (ADC) ADC Channel Data Register 4
#define ADC_CDR2 (*AT91C_ADC_CDR2) // (ADC) ADC Channel Data Register 2
#define ADC_CDR0 (*AT91C_ADC_CDR0) // (ADC) ADC Channel Data Register 0
#define ADC_CDR7 (*AT91C_ADC_CDR7) // (ADC) ADC Channel Data Register 7
#define ADC_CDR1 (*AT91C_ADC_CDR1) // (ADC) ADC Channel Data Register 1
#define ADC_CDR3 (*AT91C_ADC_CDR3) // (ADC) ADC Channel Data Register 3
#define ADC_CDR5 (*AT91C_ADC_CDR5) // (ADC) ADC Channel Data Register 5
#define ADC_MR (*AT91C_ADC_MR) // (ADC) ADC Mode Register
#define ADC_CDR6 (*AT91C_ADC_CDR6) // (ADC) ADC Channel Data Register 6
#define ADC_CR (*AT91C_ADC_CR) // (ADC) ADC Control Register
#define ADC_CHER (*AT91C_ADC_CHER) // (ADC) ADC Channel Enable Register
#define ADC_CHSR (*AT91C_ADC_CHSR) // (ADC) ADC Channel Status Register
#define ADC_IER (*AT91C_ADC_IER) // (ADC) ADC Interrupt Enable Register
#define ADC_SR (*AT91C_ADC_SR) // (ADC) ADC Status Register
#define ADC_CHDR (*AT91C_ADC_CHDR) // (ADC) ADC Channel Disable Register
#define ADC_IDR (*AT91C_ADC_IDR) // (ADC) ADC Interrupt Disable Register
#define ADC_LCDR (*AT91C_ADC_LCDR) // (ADC) ADC Last Converted Data Register
// ========== Register definition for PDC_SSC peripheral ==========
#define SSC_PTCR (*AT91C_SSC_PTCR) // (PDC_SSC) PDC Transfer Control Register
#define SSC_TNPR (*AT91C_SSC_TNPR) // (PDC_SSC) Transmit Next Pointer Register
#define SSC_RNPR (*AT91C_SSC_RNPR) // (PDC_SSC) Receive Next Pointer Register
#define SSC_TPR (*AT91C_SSC_TPR) // (PDC_SSC) Transmit Pointer Register
#define SSC_RPR (*AT91C_SSC_RPR) // (PDC_SSC) Receive Pointer Register
#define SSC_PTSR (*AT91C_SSC_PTSR) // (PDC_SSC) PDC Transfer Status Register
#define SSC_TNCR (*AT91C_SSC_TNCR) // (PDC_SSC) Transmit Next Counter Register
#define SSC_RNCR (*AT91C_SSC_RNCR) // (PDC_SSC) Receive Next Counter Register
#define SSC_TCR (*AT91C_SSC_TCR) // (PDC_SSC) Transmit Counter Register
#define SSC_RCR (*AT91C_SSC_RCR) // (PDC_SSC) Receive Counter Register
// ========== Register definition for SSC peripheral ==========
#define SSC_RFMR (*AT91C_SSC_RFMR) // (SSC) Receive Frame Mode Register
#define SSC_CMR (*AT91C_SSC_CMR) Clock Mode Register
#define SSC_IDR (*AT91C_SSC_IDR) // (SSC) Interrupt Disable Register
#define SSC_SR (*AT91C_SSC_SR) // (SSC) Status Register
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