microrom_mod.vhd

debussy中文使用手册

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: microrom.v
--   description: This part modelize the mapping rom

--                addr: 8-bits address bus
--                data: 8-bits data bus
--                addr_error: address out of range


library IEEE;
use STD.STANDARD.all;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use work.packageCPU.all;

entity rom0 is
port (
        addr : in std_logic_vector(7 downto 0);
        dout : out std_logic_vector(21 downto 0);
        addr_error : out std_logic);
end rom0;

architecture behav of rom0 is
    type Mem_Type is array (0 to 2**addr'length-1)
                of std_logic_vector(dout'range);
    signal mem : Mem_Type;
---    signal addr_i      : integer :=0;
begin
  microrom0: process (addr)

    FILE instuff : TEXT is IN "./vhdl/memory/microrom.dat";

    variable Initialization : boolean := true;
    variable InLine         : line;
    variable memaddr        : integer := 0;
    variable Word           : bit_vector(dout'range);

  begin
    if Initialization then
      File_Read : while not Endfile(instuff) loop
        ReadLine(instuff, InLine);
        next File_Read when InLine'length = 0;        -- empty line

        read(InLine,Word);
        mem(memaddr) <= To_StdLogicVector(Word);
        memaddr := memaddr + 1;
      end loop File_Read;
      Initialization := false;
    end if;

    dout <= mem(to_natural(addr));
    if ((to_natural(addr) > 255) or (to_natural(addr) < 0)) then
      addr_error <= '1';
    else
      addr_error <= '0';
    end if;
  end process microrom0;
end behav;