arithlogic.vhd

debussy中文使用手册

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: alu.v
--   description: this parts perform the arithmetic and login funtion
--                which is defined by mode select

--                a,b: operand data inputs
--                cin: carry input
--                select: alu function select
--                dout: alu result data output
--                carry: alu result carry output
--                zero: alu result zero output


library IEEE;
use std.standard.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use IEEE.std_logic_signed.all;
use work.packageCPU.all;
use work.functions.all;


entity alulogic is
    port (
        a : in std_logic_vector(7 downto 0);
        b : in std_logic_vector(7 downto 0);
        cin : in std_logic;
        sel : in std_logic_vector(2 downto 0);
        o : buffer std_logic_vector(7 downto 0);
        carry : out std_logic;
        zero : out std_logic);
end alulogic;

architecture RTL of alulogic is
begin
  process(a,b,cin,sel)
  begin
    case sel is
      when "000" => o <= unsigned(a) + unsigned(b) + cin after 1 ns;
      when "001" => o <= unsigned(a) - unsigned(b) + cin after 1 ns;
      when "010" => o <= unsigned(a) - unsigned(b) - cin after 1 ns;
      when "011" => o <= a and b after 1 ns;
      when "100" => o <= a or b after 1 ns;
      when "101" => o <= a xor b after 1 ns;
      when "110" => o <= a xor b after 1 ns;
      when others => o <= (others => '0');
    end case;
  end process;

  carry <= a(7) and b(7);


  process(o)
  begin
	if (is_zero(o)) then
		zero <= '1' ;
	else
		zero <= '0';
	end if;
  end process;
end RTL;