fsm_child3g.vhd

debussy中文使用手册

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_FSM_CHILD3 is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_FSM_CHILD3;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_FSM_CHILD3.all;

entity FSM_CHILD3 is

   port( Clock, Reset, TwoOnly, StartFSM3 : in std_logic;  Mux3_Sel : out 
         std_logic_vector (1 downto 0));

end FSM_CHILD3;

architecture SYN_RTL of FSM_CHILD3 is

   component INR2D0
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component AOI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFF1Q
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal Mux3_Sel_0_port, CurrStateFSM396_0_port, Mux3_Sel_1_port, 
      CurrStateFSM396_1_port, n105, n106, n107 : std_logic;

begin
   Mux3_Sel <= ( Mux3_Sel_1_port, Mux3_Sel_0_port );
   
   U33 : INR2D0 port map( A1 => n105, B1 => n106, ZN => CurrStateFSM396_1_port)
                           ;
   U34 : AN3D1 port map( A1 => StartFSM3, A2 => n107, A3 => n105, Z => 
                           CurrStateFSM396_0_port);
   U35 : AOI21D0 port map( A1 => StartFSM3, A2 => TwoOnly, B => Mux3_Sel_0_port
                           , ZN => n106);
   U36 : NR2D0 port map( A1 => Reset, A2 => Mux3_Sel_1_port, ZN => n105);
   U37 : INV0 port map( I => Mux3_Sel_0_port, ZN => n107);
   CurrStateFSM3_reg_0_label : DFF1Q port map( D => CurrStateFSM396_0_port, CP 
                           => Clock, Q => Mux3_Sel_0_port);
   CurrStateFSM3_reg_1_label : DFF1Q port map( D => CurrStateFSM396_1_port, CP 
                           => Clock, Q => Mux3_Sel_1_port);

end SYN_RTL;