cpug.vhd

debussy中文使用手册

                           , dout(2) => rom_out_2_port, dout(1) => 
                           rom_out_1_port, dout(0) => rom_out_0_port, 
                           addr_error => n508);
   U198 : INV3 port map( I => clock, ZN => n490);
   C1_reg : DFCN2 port map( D => mprom_out_1_port, CP => n490, CDN => reset, Q 
                           => C1, QN => n509);
   U199 : MOAI22D0 port map( A1 => net282, A2 => n500, B1 => n501, B2 => 
                           rom_out_7_port, ZN => MA_7_port);
   U200 : MOAI22D0 port map( A1 => n500, A2 => net283, B1 => rom_out_6_port, B2
                           => n501, ZN => MA_6_port);
   U201 : MOAI22D0 port map( A1 => n500, A2 => net284, B1 => rom_out_5_port, B2
                           => n501, ZN => MA_5_port);
   U202 : MOAI22D0 port map( A1 => n500, A2 => net285, B1 => rom_out_4_port, B2
                           => n501, ZN => MA_4_port);
   U203 : MOAI22D0 port map( A1 => n500, A2 => net286, B1 => rom_out_3_port, B2
                           => n501, ZN => MA_3_port);
   U204 : MOAI22D0 port map( A1 => n500, A2 => net287, B1 => rom_out_2_port, B2
                           => n501, ZN => MA_2_port);
   U205 : MOAI22D0 port map( A1 => n500, A2 => net288, B1 => rom_out_1_port, B2
                           => n501, ZN => MA_1_port);
   U206 : MOAI22D0 port map( A1 => n500, A2 => net289, B1 => rom_out_0_port, B2
                           => n501, ZN => MA_0_port);
   U207 : INV0 port map( I => mprom_out_11_port, ZN => n502);
   U208 : INV0 port map( I => mprom_out_10_port, ZN => n503);
   U209 : INV0 port map( I => mprom_out_9_port, ZN => n504);
   U210 : INV0 port map( I => mprom_out_8_port, ZN => n505);
   U211 : INV0 port map( I => mprom_out_7_port, ZN => n506);
   U212 : ND3D0 port map( A1 => C21, A2 => C20, A3 => reset, ZN => n500);
   U213 : AN3D1 port map( A1 => C20, A2 => n499, A3 => reset, Z => n501);
   next_MA_reg_7_label : DFCN1 port map( D => X_return170_7_port, CP => n490, 
                           CDN => reset, Q => n510, QN => net282);
   next_MA_reg_6_label : DFCN1 port map( D => X_return170_6_port, CP => n490, 
                           CDN => reset, Q => n511, QN => net283);
   next_MA_reg_5_label : DFCN1 port map( D => X_return170_5_port, CP => n490, 
                           CDN => reset, Q => n512, QN => net284);
   next_MA_reg_4_label : DFCN1 port map( D => X_return170_4_port, CP => n490, 
                           CDN => reset, Q => n513, QN => net285);
   next_MA_reg_3_label : DFCN1 port map( D => X_return170_3_port, CP => n490, 
                           CDN => reset, Q => n514, QN => net286);
   next_MA_reg_2_label : DFCN1 port map( D => X_return170_2_port, CP => n490, 
                           CDN => reset, Q => n515, QN => net287);
   next_MA_reg_1_label : DFCN1 port map( D => X_return170_1_port, CP => n490, 
                           CDN => reset, Q => n516, QN => net288);
   next_MA_reg_0_label : DFCN1 port map( D => X_return170_0_port, CP => n490, 
                           CDN => reset, Q => n517, QN => net289);
   mux_sel_reg_2_label : DFCN1 port map( D => mprom_out_4_port, CP => n490, CDN
                           => reset, Q => mux_sel(2), QN => n518);
   mux_sel_reg_1_label : DFCN1 port map( D => mprom_out_3_port, CP => n490, CDN
                           => reset, Q => mux_sel(1), QN => n519);
   mux_sel_reg_0_label : DFCN1 port map( D => mprom_out_2_port, CP => n490, CDN
                           => reset, Q => mux_sel(0), QN => n520);
   CH_reg_4_label : DFCN1 port map( D => n502, CP => n490, CDN => reset, Q => 
                           CH(4), QN => n521);
   CH_reg_3_label : DFCN1 port map( D => n503, CP => n490, CDN => reset, Q => 
                           CH(3), QN => n522);
   CH_reg_2_label : DFCN1 port map( D => n504, CP => n490, CDN => reset, Q => 
                           CH(2), QN => n523);
   CH_reg_1_label : DFCN1 port map( D => n505, CP => n490, CDN => reset, Q => 
                           CH(1), QN => n524);
   CH_reg_0_label : DFCN1 port map( D => n506, CP => n490, CDN => reset, Q => 
                           CH(0), QN => n525);
   alu_mode_reg_2_label : DFCN1 port map( D => mprom_out_14_port, CP => n490, 
                           CDN => reset, Q => alu_mode(2), QN => n526);
   alu_mode_reg_1_label : DFCN1 port map( D => mprom_out_13_port, CP => n490, 
                           CDN => reset, Q => alu_mode(1), QN => n527);
   alu_mode_reg_0_label : DFCN1 port map( D => mprom_out_12_port, CP => n490, 
                           CDN => reset, Q => alu_mode(0), QN => n528);
   bus_mode_reg_2_label : DFCN1 port map( D => mprom_out_17_port, CP => n490, 
                           CDN => reset, Q => bus_mode(2), QN => n529);
   bus_mode_reg_1_label : DFCN1 port map( D => mprom_out_16_port, CP => n490, 
                           CDN => reset, Q => bus_mode(1), QN => n530);
   bus_mode_reg_0_label : DFCN1 port map( D => mprom_out_15_port, CP => n490, 
                           CDN => reset, Q => bus_mode(0), QN => n531);
   C21_reg : DFCN1 port map( D => mprom_out_21_port, CP => n490, CDN => reset, 
                           Q => C21, QN => n499);
   C5_reg : DFCN1 port map( D => mprom_out_5_port, CP => n490, CDN => reset, Q 
                           => C5, QN => n532);
   carry_mode_reg : DFCN1 port map( D => mprom_out_18_port, CP => n490, CDN => 
                           reset, Q => carry_mode, QN => n533);
   C20_reg : DFCN1 port map( D => mprom_out_20_port, CP => n490, CDN => reset, 
                           Q => C20, QN => n534);
   C0_reg : DFCN1 port map( D => mprom_out_0_port, CP => n490, CDN => reset, Q 
                           => C0, QN => n535);
   C19_reg : DFCN1 port map( D => mprom_out_19_port, CP => n490, CDN => reset, 
                           Q => C19, QN => n536);
   C6_reg : DFCN1 port map( D => mprom_out_6_port, CP => n490, CDN => reset, Q 
                           => C6, QN => n537);
   IR_reg_1_label : DFCN1Q port map( D => TDB(1), CP => C19, CDN => reset, Q =>
                           IR(1));
   IR_reg_0_label : DFCN1Q port map( D => TDB(0), CP => C19, CDN => reset, Q =>
                           IR(0));
   IR7_IR2_reg_5_label : DFCN1Q port map( D => TDB(7), CP => C19, CDN => reset,
                           Q => IR7_IR2_5_port);
   IR7_IR2_reg_4_label : DFCN1Q port map( D => TDB(6), CP => C19, CDN => reset,
                           Q => IR7_IR2_4_port);
   IR7_IR2_reg_3_label : DFCN1Q port map( D => TDB(5), CP => C19, CDN => reset,
                           Q => IR7_IR2_3_port);
   IR7_IR2_reg_2_label : DFCN1Q port map( D => TDB(4), CP => C19, CDN => reset,
                           Q => IR7_IR2_2_port);
   IR7_IR2_reg_1_label : DFCN1Q port map( D => TDB(3), CP => C19, CDN => reset,
                           Q => IR7_IR2_1_port);
   IR7_IR2_reg_0_label : DFCN1Q port map( D => TDB(2), CP => C19, CDN => reset,
                           Q => IR7_IR2_0_port);
   add_122_plus : CCU_DW01_inc_8_0 port map( A(7) => MA_7_port, A(6) => 
                           MA_6_port, A(5) => MA_5_port, A(4) => MA_4_port, 
                           A(3) => MA_3_port, A(2) => MA_2_port, A(1) => 
                           MA_1_port, A(0) => MA_0_port, SUM(7) => 
                           X_return170_7_port, SUM(6) => X_return170_6_port, 
                           SUM(5) => X_return170_5_port, SUM(4) => 
                           X_return170_4_port, SUM(3) => X_return170_3_port, 
                           SUM(2) => X_return170_2_port, SUM(1) => 
                           X_return170_1_port, SUM(0) => X_return170_0_port);

end SYN_RTL_architecture2;
library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity CPU is

   port( clock, reset : in std_logic;  VMA, R_W : out std_logic;  addr : out 
         std_logic_vector (7 downto 0);  data : inout std_logic_vector (7 
         downto 0));

end CPU;

architecture SYN_BLK of CPU is

   component ALUB
      port( IR : in std_logic_vector (1 downto 0);  IDB, PC : in 
            std_logic_vector (7 downto 0);  clock, reset : in std_logic;  S1 : 
            buffer std_logic;  ALU, IXR : buffer std_logic_vector (7 downto 0);
            bus_mode, alu_mode : in std_logic_vector (2 downto 0);  carry_mode 
            : in std_logic;  error_out : out std_logic;  CH : in 
            std_logic_vector (4 downto 0));
   end component;
   
   component PCU
      port( ALU, IXR : in std_logic_vector (7 downto 0);  PC, IDB : buffer 
            std_logic_vector (7 downto 0);  data : inout std_logic_vector (7 
            downto 0);  TDB : buffer std_logic_vector (7 downto 0);  S1, 
            error_in, C6, C5, C1 : in std_logic;  mux_sel : in std_logic_vector
            (2 downto 0);  reset : in std_logic);
   end component;
   
   component CCU
      port( TDB : in std_logic_vector (7 downto 0);  clock, reset : in 
            std_logic;  CH : out std_logic_vector (4 downto 0);  IR : out 
            std_logic_vector (1 downto 0);  alu_mode, bus_mode : out 
            std_logic_vector (2 downto 0);  carry_mode : out std_logic;  
            mux_sel : out std_logic_vector (2 downto 0);  C6, C5, C1, C0 : out 
            std_logic);
   end component;
   
   signal n_IR0_1_port, n_CH0_1_port, n_ALU0_6_port, n_ALU0_2_port, R_W_port, 
      n_C60, n_ALU0_0_port, n_mux_sel0_1_port, n_CH0_2_port, n_bus_mode0_1_port
      , n_PC0_0_port, addr_0_port, n_CH0_3_port, n_ALU0_4_port, 
      n_alu_mode0_0_port, n_TDB0_0_port, addr_4_port, n_PC0_4_port, 
      n_IXR0_7_port, n_carry_mode0, n_IXR0_3_port, n_TDB0_4_port, 
      n_bus_mode0_0_port, n_IXR0_5_port, addr_6_port, n_PC0_6_port, 
      n_IXR0_1_port, n_TDB0_6_port, n_IXR0_4_port, addr_2_port, n_S10, 
      n_PC0_2_port, n_alu_mode0_2_port, n_TDB0_2_port, n_error_out0, 
      addr_3_port, n_PC0_3_port, n_TDB0_3_port, n_bus_mode0_2_port, addr_7_port
      , n_PC0_7_port, n_IXR0_0_port, n_TDB0_7_port, addr_5_port, n_PC0_5_port, 
      n_IXR0_2_port, n_TDB0_5_port, n_PC0_1_port, addr_1_port, 
      n_alu_mode0_1_port, n_TDB0_1_port, n_ALU0_5_port, n_IXR0_6_port, 
      n_IR0_0_port, n_CH0_4_port, n_ALU0_1_port, n_C50, n_mux_sel0_0_port, 
      n_CH0_0_port, n_ALU0_7_port, n_ALU0_3_port, n_mux_sel0_2_port : std_logic
      ;

begin
   R_W <= R_W_port;
   addr <= ( addr_7_port, addr_6_port, addr_5_port, addr_4_port, addr_3_port, 
      addr_2_port, addr_1_port, addr_0_port );
   
   i_ALUB : ALUB port map( IR(1) => n_IR0_1_port, IR(0) => n_IR0_0_port, IDB(7)
                           => addr_7_port, IDB(6) => addr_6_port, IDB(5) => 
                           addr_5_port, IDB(4) => addr_4_port, IDB(3) => 
                           addr_3_port, IDB(2) => addr_2_port, IDB(1) => 
                           addr_1_port, IDB(0) => addr_0_port, PC(7) => 
                           n_PC0_7_port, PC(6) => n_PC0_6_port, PC(5) => 
                           n_PC0_5_port, PC(4) => n_PC0_4_port, PC(3) => 
                           n_PC0_3_port, PC(2) => n_PC0_2_port, PC(1) => 
                           n_PC0_1_port, PC(0) => n_PC0_0_port, clock => clock,
                           reset => reset, S1 => n_S10, ALU(7) => n_ALU0_7_port
                           , ALU(6) => n_ALU0_6_port, ALU(5) => n_ALU0_5_port, 
                           ALU(4) => n_ALU0_4_port, ALU(3) => n_ALU0_3_port, 
                           ALU(2) => n_ALU0_2_port, ALU(1) => n_ALU0_1_port, 
                           ALU(0) => n_ALU0_0_port, IXR(7) => n_IXR0_7_port, 
                           IXR(6) => n_IXR0_6_port, IXR(5) => n_IXR0_5_port, 
                           IXR(4) => n_IXR0_4_port, IXR(3) => n_IXR0_3_port, 
                           IXR(2) => n_IXR0_2_port, IXR(1) => n_IXR0_1_port, 
                           IXR(0) => n_IXR0_0_port, bus_mode(2) => 
                           n_bus_mode0_2_port, bus_mode(1) => 
                           n_bus_mode0_1_port, bus_mode(0) => 
                           n_bus_mode0_0_port, alu_mode(2) => 
                           n_alu_mode0_2_port, alu_mode(1) => 
                           n_alu_mode0_1_port, alu_mode(0) => 
                           n_alu_mode0_0_port, carry_mode => n_carry_mode0, 
                           error_out => n_error_out0, CH(4) => n_CH0_4_port, 
                           CH(3) => n_CH0_3_port, CH(2) => n_CH0_2_port, CH(1) 
                           => n_CH0_1_port, CH(0) => n_CH0_0_port);
   i_PCU : PCU port map( ALU(7) => n_ALU0_7_port, ALU(6) => n_ALU0_6_port, 
                           ALU(5) => n_ALU0_5_port, ALU(4) => n_ALU0_4_port, 
                           ALU(3) => n_ALU0_3_port, ALU(2) => n_ALU0_2_port, 
                           ALU(1) => n_ALU0_1_port, ALU(0) => n_ALU0_0_port, 
                           IXR(7) => n_IXR0_7_port, IXR(6) => n_IXR0_6_port, 
                           IXR(5) => n_IXR0_5_port, IXR(4) => n_IXR0_4_port, 
                           IXR(3) => n_IXR0_3_port, IXR(2) => n_IXR0_2_port, 
                           IXR(1) => n_IXR0_1_port, IXR(0) => n_IXR0_0_port, 
                           PC(7) => n_PC0_7_port, PC(6) => n_PC0_6_port, PC(5) 
                           => n_PC0_5_port, PC(4) => n_PC0_4_port, PC(3) => 
                           n_PC0_3_port, PC(2) => n_PC0_2_port, PC(1) => 
                           n_PC0_1_port, PC(0) => n_PC0_0_port, IDB(7) => 
                           addr_7_port, IDB(6) => addr_6_port, IDB(5) => 
                           addr_5_port, IDB(4) => addr_4_port, IDB(3) => 
                           addr_3_port, IDB(2) => addr_2_port, IDB(1) => 
                           addr_1_port, IDB(0) => addr_0_port, data(7) => 
                           data(7), data(6) => data(6), data(5) => data(5), 
                           data(4) => data(4), data(3) => data(3), data(2) => 
                           data(2), data(1) => data(1), data(0) => data(0), 
                           TDB(7) => n_TDB0_7_port, TDB(6) => n_TDB0_6_port, 
                           TDB(5) => n_TDB0_5_port, TDB(4) => n_TDB0_4_port, 
                           TDB(3) => n_TDB0_3_port, TDB(2) => n_TDB0_2_port, 
                           TDB(1) => n_TDB0_1_port, TDB(0) => n_TDB0_0_port, S1
                           => n_S10, error_in => n_error_out0, C6 => n_C60, C5 
                           => n_C50, C1 => R_W_port, mux_sel(2) => 
                           n_mux_sel0_2_port, mux_sel(1) => n_mux_sel0_1_port, 
                           mux_sel(0) => n_mux_sel0_0_port, reset => reset);
   i_CCU : CCU port map( TDB(7) => n_TDB0_7_port, TDB(6) => n_TDB0_6_port, 
                           TDB(5) => n_TDB0_5_port, TDB(4) => n_TDB0_4_port, 
                           TDB(3) => n_TDB0_3_port, TDB(2) => n_TDB0_2_port, 
                           TDB(1) => n_TDB0_1_port, TDB(0) => n_TDB0_0_port, 
                           clock => clock, reset => reset, CH(4) => 
                           n_CH0_4_port, CH(3) => n_CH0_3_port, CH(2) => 
                           n_CH0_2_port, CH(1) => n_CH0_1_port, CH(0) => 
                           n_CH0_0_port, IR(1) => n_IR0_1_port, IR(0) => 
                           n_IR0_0_port, alu_mode(2) => n_alu_mode0_2_port, 
                           alu_mode(1) => n_alu_mode0_1_port, alu_mode(0) => 
                           n_alu_mode0_0_port, bus_mode(2) => 
                           n_bus_mode0_2_port, bus_mode(1) => 
                           n_bus_mode0_1_port, bus_mode(0) => 
                           n_bus_mode0_0_port, carry_mode => n_carry_mode0, 
                           mux_sel(2) => n_mux_sel0_2_port, mux_sel(1) => 
                           n_mux_sel0_1_port, mux_sel(0) => n_mux_sel0_0_port, 
                           C6 => n_C60, C5 => n_C50, C1 => R_W_port, C0 => VMA)
                           ;

end SYN_BLK;