cpug.vhd

debussy中文使用手册

                           ZN => n418);
   U209 : AOI22D0 port map( A1 => n422, A2 => IDR_5_port, B1 => TR_5_port, B2 
                           => n426, ZN => n415);
   U210 : AOI22D0 port map( A1 => ALU(5), A2 => n427, B1 => IXR(5), B2 => n428,
                           ZN => n416);
   U211 : AOI22D0 port map( A1 => n422, A2 => IDR_4_port, B1 => TR_4_port, B2 
                           => n426, ZN => n413);
   U212 : AOI22D0 port map( A1 => ALU(4), A2 => n427, B1 => IXR(4), B2 => n428,
                           ZN => n414);
   U213 : AOI22D0 port map( A1 => n422, A2 => IDR_3_port, B1 => TR_3_port, B2 
                           => n426, ZN => n411);
   U214 : AOI22D0 port map( A1 => ALU(3), A2 => n427, B1 => IXR(3), B2 => n428,
                           ZN => n412);
   U215 : AOI22D0 port map( A1 => n422, A2 => IDR_2_port, B1 => TR_2_port, B2 
                           => n426, ZN => n409);
   U216 : AOI22D0 port map( A1 => ALU(2), A2 => n427, B1 => IXR(2), B2 => n428,
                           ZN => n410);
   U217 : AOI22D0 port map( A1 => n422, A2 => IDR_1_port, B1 => TR_1_port, B2 
                           => n426, ZN => n407);
   U218 : AOI22D0 port map( A1 => ALU(1), A2 => n427, B1 => IXR(1), B2 => n428,
                           ZN => n408);
   U219 : AOI22D0 port map( A1 => n422, A2 => IDR_0_port, B1 => TR_0_port, B2 
                           => n426, ZN => n405);
   U220 : AOI22D0 port map( A1 => ALU(0), A2 => n427, B1 => IXR(0), B2 => n428,
                           ZN => n406);
   IDR_reg_7_label : DFCN1 port map( D => n429, CP => n392, CDN => reset, Q => 
                           IDR_7_port, QN => n403);
   IDR_reg_6_label : DFCN1 port map( D => n430, CP => n392, CDN => reset, Q => 
                           IDR_6_port, QN => n396);
   IDR_reg_5_label : DFCN1 port map( D => n431, CP => n392, CDN => reset, Q => 
                           IDR_5_port, QN => n400);
   IDR_reg_4_label : DFCN1 port map( D => n432, CP => n392, CDN => reset, Q => 
                           IDR_4_port, QN => n399);
   IDR_reg_3_label : DFCN1 port map( D => n433, CP => n392, CDN => reset, Q => 
                           IDR_3_port, QN => n402);
   IDR_reg_2_label : DFCN1 port map( D => n434, CP => n392, CDN => reset, Q => 
                           IDR_2_port, QN => n397);
   IDR_reg_1_label : DFCN1 port map( D => n435, CP => n392, CDN => reset, Q => 
                           IDR_1_port, QN => n401);
   IDR_reg_0_label : DFCN1 port map( D => n436, CP => n392, CDN => reset, Q => 
                           IDR_0_port, QN => n398);
   PC_reg_7_label : DFCN1 port map( D => ALU(7), CP => n378, CDN => reset, Q =>
                           PC_7_port, QN => net168);
   PC_reg_6_label : DFCN1 port map( D => ALU(6), CP => n378, CDN => reset, Q =>
                           PC_6_port, QN => net169);
   PC_reg_5_label : DFCN1 port map( D => ALU(5), CP => n378, CDN => reset, Q =>
                           PC_5_port, QN => net170);
   PC_reg_4_label : DFCN1 port map( D => ALU(4), CP => n378, CDN => reset, Q =>
                           PC_4_port, QN => net171);
   PC_reg_3_label : DFCN1 port map( D => ALU(3), CP => n378, CDN => reset, Q =>
                           PC_3_port, QN => net172);
   PC_reg_2_label : DFCN1 port map( D => ALU(2), CP => n378, CDN => reset, Q =>
                           PC_2_port, QN => net173);
   PC_reg_1_label : DFCN1 port map( D => ALU(1), CP => n378, CDN => reset, Q =>
                           PC_1_port, QN => net174);
   PC_reg_0_label : DFCN1 port map( D => ALU(0), CP => n378, CDN => reset, Q =>
                           PC_0_port, QN => net175);
   TR_reg_7_label : DFCN1 port map( D => ALU(7), CP => n_clk1, CDN => reset, Q 
                           => TR_7_port, QN => n437);
   TR_reg_6_label : DFCN1 port map( D => ALU(6), CP => n_clk1, CDN => reset, Q 
                           => TR_6_port, QN => n438);
   TR_reg_5_label : DFCN1 port map( D => ALU(5), CP => n_clk1, CDN => reset, Q 
                           => TR_5_port, QN => n439);
   TR_reg_4_label : DFCN1 port map( D => ALU(4), CP => n_clk1, CDN => reset, Q 
                           => TR_4_port, QN => n440);
   TR_reg_3_label : DFCN1 port map( D => ALU(3), CP => n_clk1, CDN => reset, Q 
                           => TR_3_port, QN => n441);
   TR_reg_2_label : DFCN1 port map( D => ALU(2), CP => n_clk1, CDN => reset, Q 
                           => TR_2_port, QN => n442);
   TR_reg_1_label : DFCN1 port map( D => ALU(1), CP => n_clk1, CDN => reset, Q 
                           => TR_1_port, QN => n443);
   TR_reg_0_label : DFCN1 port map( D => ALU(0), CP => n_clk1, CDN => reset, Q 
                           => TR_0_port, QN => n444);
   TDB_reg_7_label : LH1 port map( E => n_589, D => n_574, Q => TDB_7_port, QN 
                           => n445);
   TDB_reg_6_label : LH1 port map( E => n_589, D => n_575, Q => TDB_6_port, QN 
                           => n446);
   TDB_reg_5_label : LH1 port map( E => n_589, D => n_576, Q => TDB_5_port, QN 
                           => n447);
   TDB_reg_4_label : LH1 port map( E => n_589, D => n_577, Q => TDB_4_port, QN 
                           => n448);
   TDB_reg_3_label : LH1 port map( E => n_589, D => n_578, Q => TDB_3_port, QN 
                           => n449);
   TDB_reg_2_label : LH1 port map( E => n_589, D => n_579, Q => TDB_2_port, QN 
                           => n450);
   TDB_reg_1_label : LH1 port map( E => n_589, D => n_580, Q => TDB_1_port, QN 
                           => n451);
   TDB_reg_0_label : LH1 port map( E => n_589, D => n_581, Q => TDB_0_port, QN 
                           => n452);

end SYN_RTL_architecture;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity CCU_DW01_inc_8_0 is

   port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector (7 
         downto 0));

end CCU_DW01_inc_8_0;

architecture SYN_rpl of CCU_DW01_inc_8_0 is

   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component XOR2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component HA1D1
      port( A, B : in std_logic;  S, CO : out std_logic);
   end component;
   
   signal carry_4_port, carry_2_port, carry_6_port, carry_7_port, carry_3_port,
      carry_5_port : std_logic;

begin
   
   U5 : INV0 port map( I => A(0), ZN => SUM(0));
   U6 : XOR2D1 port map( A1 => A(7), A2 => carry_7_port, Z => SUM(7));
   U1_1_3 : HA1D1 port map( A => A(3), B => carry_3_port, S => SUM(3), CO => 
                           carry_4_port);
   U1_1_4 : HA1D1 port map( A => A(4), B => carry_4_port, S => SUM(4), CO => 
                           carry_5_port);
   U1_1_1 : HA1D1 port map( A => A(1), B => A(0), S => SUM(1), CO => 
                           carry_2_port);
   U1_1_2 : HA1D1 port map( A => A(2), B => carry_2_port, S => SUM(2), CO => 
                           carry_3_port);
   U1_1_5 : HA1D1 port map( A => A(5), B => carry_5_port, S => SUM(5), CO => 
                           carry_6_port);
   U1_1_6 : HA1D1 port map( A => A(6), B => carry_6_port, S => SUM(6), CO => 
                           carry_7_port);

end SYN_rpl;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity CCU is

   port( TDB : in std_logic_vector (7 downto 0);  clock, reset : in std_logic; 
         CH : out std_logic_vector (4 downto 0);  IR : out std_logic_vector (1 
         downto 0);  alu_mode, bus_mode : out std_logic_vector (2 downto 0);  
         carry_mode : out std_logic;  mux_sel : out std_logic_vector (2 downto 
         0);  C6, C5, C1, C0 : out std_logic);

end CCU;

architecture SYN_RTL_architecture2 of CCU is

   component rom
      port( addr : in std_logic_vector (5 downto 0);  dout : out 
            std_logic_vector (7 downto 0);  addr_error : out std_logic);
   end component;
   
   component rom0
      port( addr : in std_logic_vector (7 downto 0);  dout : out 
            std_logic_vector (21 downto 0);  addr_error : out std_logic);
   end component;
   
   component INV3
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFCN2
      port( D, CP, CDN : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component MOAI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component DFCN1
      port( D, CP, CDN : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component DFCN1Q
      port( D, CP, CDN : in std_logic;  Q : out std_logic);
   end component;
   
   component CCU_DW01_inc_8_0
      port( A : in std_logic_vector (7 downto 0);  SUM : out std_logic_vector 
            (7 downto 0));
   end component;
   
   signal X_return170_3_port, MA_1_port, X_return170_7_port, MA_5_port, C21, 
      MA_7_port, X_return170_5_port, MA_3_port, X_return170_1_port, 
      rom_out_4_port, mprom_out_21_port, mprom_out_12_port, IR7_IR2_4_port, C20
      , mprom_out_4_port, mprom_out_16_port, IR7_IR2_0_port, rom_out_0_port, 
      mprom_out_9_port, mprom_out_0_port, mprom_out_2_port, rom_out_2_port, 
      mprom_out_14_port, IR7_IR2_2_port, mprom_out_6_port, mprom_out_19_port, 
      rom_out_6_port, mprom_out_10_port, mprom_out_7_port, mprom_out_18_port, 
      mprom_out_11_port, rom_out_7_port, C19, mprom_out_3_port, rom_out_3_port,
      mprom_out_15_port, IR7_IR2_3_port, mprom_out_17_port, IR7_IR2_1_port, 
      rom_out_1_port, mprom_out_8_port, mprom_out_1_port, rom_out_5_port, 
      mprom_out_13_port, mprom_out_20_port, IR7_IR2_5_port, mprom_out_5_port, 
      MA_2_port, X_return170_0_port, MA_6_port, X_return170_4_port, 
      X_return170_6_port, MA_4_port, X_return170_2_port, MA_0_port, n490, n499,
      n500, n501, net282, net283, net284, net285, net286, net287, net288, 
      net289, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
      n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, 
      n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, 
      n537 : std_logic;

begin
   
   i_rom0 : rom0 port map( addr(7) => MA_7_port, addr(6) => MA_6_port, addr(5) 
                           => MA_5_port, addr(4) => MA_4_port, addr(3) => 
                           MA_3_port, addr(2) => MA_2_port, addr(1) => 
                           MA_1_port, addr(0) => MA_0_port, dout(21) => 
                           mprom_out_21_port, dout(20) => mprom_out_20_port, 
                           dout(19) => mprom_out_19_port, dout(18) => 
                           mprom_out_18_port, dout(17) => mprom_out_17_port, 
                           dout(16) => mprom_out_16_port, dout(15) => 
                           mprom_out_15_port, dout(14) => mprom_out_14_port, 
                           dout(13) => mprom_out_13_port, dout(12) => 
                           mprom_out_12_port, dout(11) => mprom_out_11_port, 
                           dout(10) => mprom_out_10_port, dout(9) => 
                           mprom_out_9_port, dout(8) => mprom_out_8_port, 
                           dout(7) => mprom_out_7_port, dout(6) => 
                           mprom_out_6_port, dout(5) => mprom_out_5_port, 
                           dout(4) => mprom_out_4_port, dout(3) => 
                           mprom_out_3_port, dout(2) => mprom_out_2_port, 
                           dout(1) => mprom_out_1_port, dout(0) => 
                           mprom_out_0_port, addr_error => n507);
   i_rom : rom port map( addr(5) => IR7_IR2_5_port, addr(4) => IR7_IR2_4_port, 
                           addr(3) => IR7_IR2_3_port, addr(2) => IR7_IR2_2_port
                           , addr(1) => IR7_IR2_1_port, addr(0) => 
                           IR7_IR2_0_port, dout(7) => rom_out_7_port, dout(6) 
                           => rom_out_6_port, dout(5) => rom_out_5_port, 
                           dout(4) => rom_out_4_port, dout(3) => rom_out_3_port