cpug.vhd

debussy中文使用手册

                           PC(4), ZN => n623);
   U288 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_4_port, B1 => n657, B2 =>
                           IXR_tmp_4_port, ZN => n622);
   U289 : AOI22D0 port map( A1 => IDB(3), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(3), ZN => n625);
   U290 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_3_port, B1 => n657, B2 =>
                           IXR_tmp_3_port, ZN => n624);
   U291 : AOI22D0 port map( A1 => IDB(2), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(2), ZN => n627);
   U292 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_2_port, B1 => n657, B2 =>
                           IXR_tmp_2_port, ZN => n626);
   U293 : AOI22D0 port map( A1 => IDB(1), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(1), ZN => n629);
   U294 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_1_port, B1 => n657, B2 =>
                           IXR_tmp_1_port, ZN => n628);
   U295 : AOI22D0 port map( A1 => IDB(0), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(0), ZN => n631);
   U296 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_0_port, B1 => n657, B2 =>
                           IXR_tmp_0_port, ZN => n630);
   U297 : INV0 port map( I => n652, ZN => n659);
   IXR_reg_7_label : DFCN1Q port map( D => ALU_7_port, CP => T3, CDN => reset, 
                           Q => IXR_7_port);
   IXR_reg_6_label : DFCN1Q port map( D => ALU_6_port, CP => T3, CDN => reset, 
                           Q => IXR_6_port);
   IXR_reg_5_label : DFCN1Q port map( D => n_707, CP => T3, CDN => reset, Q => 
                           IXR_5_port);
   IXR_reg_4_label : DFCN1Q port map( D => n_708, CP => T3, CDN => reset, Q => 
                           IXR_4_port);
   IXR_reg_3_label : DFCN1Q port map( D => ALU_3_port, CP => T3, CDN => reset, 
                           Q => IXR_3_port);
   IXR_reg_2_label : DFCN1Q port map( D => ALU_2_port, CP => T3, CDN => reset, 
                           Q => IXR_2_port);
   IXR_reg_1_label : DFCN1Q port map( D => ALU_1_port, CP => T3, CDN => reset, 
                           Q => IXR_1_port);
   IXR_reg_0_label : DFCN1Q port map( D => ALU_0_port, CP => T3, CDN => reset, 
                           Q => IXR_0_port);
   IXR_tmp_reg_7_label : DFCN1Q port map( D => IXR_7_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_7_port);
   IXR_tmp_reg_6_label : DFCN1Q port map( D => IXR_6_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_6_port);
   IXR_tmp_reg_5_label : DFCN1Q port map( D => IXR_5_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_5_port);
   IXR_tmp_reg_4_label : DFCN1Q port map( D => IXR_4_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_4_port);
   IXR_tmp_reg_3_label : DFCN1Q port map( D => IXR_3_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_3_port);
   IXR_tmp_reg_2_label : DFCN1Q port map( D => IXR_2_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_2_port);
   IXR_tmp_reg_1_label : DFCN1Q port map( D => IXR_1_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_1_port);
   IXR_tmp_reg_0_label : DFCN1Q port map( D => IXR_0_port, CP => clock, CDN => 
                           reset, Q => IXR_tmp_0_port);
   ACC_reg_7_label : DFCN1Q port map( D => ALU_7_port, CP => T4, CDN => reset, 
                           Q => ACC_7_port);
   ACC_reg_6_label : DFCN1Q port map( D => ALU_6_port, CP => T4, CDN => reset, 
                           Q => ACC_6_port);
   ACC_reg_5_label : DFCN1Q port map( D => n_707, CP => T4, CDN => reset, Q => 
                           ACC_5_port);
   ACC_reg_4_label : DFCN1Q port map( D => n_708, CP => T4, CDN => reset, Q => 
                           ACC_4_port);
   ACC_reg_3_label : DFCN1Q port map( D => ALU_3_port, CP => T4, CDN => reset, 
                           Q => ACC_3_port);
   ACC_reg_2_label : DFCN1Q port map( D => ALU_2_port, CP => T4, CDN => reset, 
                           Q => ACC_2_port);
   ACC_reg_1_label : DFCN1Q port map( D => ALU_1_port, CP => T4, CDN => reset, 
                           Q => ACC_1_port);
   ACC_reg_0_label : DFCN1Q port map( D => ALU_0_port, CP => T4, CDN => reset, 
                           Q => ACC_0_port);
   ACC_tmp_reg_7_label : DFCN1Q port map( D => ACC_7_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_7_port);
   ACC_tmp_reg_6_label : DFCN1Q port map( D => ACC_6_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_6_port);
   ACC_tmp_reg_5_label : DFCN1Q port map( D => ACC_5_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_5_port);
   ACC_tmp_reg_4_label : DFCN1Q port map( D => ACC_4_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_4_port);
   ACC_tmp_reg_3_label : DFCN1Q port map( D => ACC_3_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_3_port);
   ACC_tmp_reg_2_label : DFCN1Q port map( D => ACC_2_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_2_port);
   ACC_tmp_reg_1_label : DFCN1Q port map( D => ACC_1_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_1_port);
   ACC_tmp_reg_0_label : DFCN1Q port map( D => ACC_0_port, CP => clock, CDN => 
                           reset, Q => ACC_tmp_0_port);
   zero_flag_reg : DFCN1Q port map( D => Zero0, CP => T2, CDN => reset, Q => 
                           zero_flag);
   carry_flag_reg : DFCN1Q port map( D => Carry0, CP => T2, CDN => reset, Q => 
                           carry_flag);

end SYN_RTL;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity PCU is

   port( ALU, IXR : in std_logic_vector (7 downto 0);  PC, IDB : buffer 
         std_logic_vector (7 downto 0);  data : inout std_logic_vector (7 
         downto 0);  TDB : buffer std_logic_vector (7 downto 0);  S1, error_in,
         C6, C5, C1 : in std_logic;  mux_sel : in std_logic_vector (2 downto 0)
         ;  reset : in std_logic);

end PCU;

architecture SYN_RTL_architecture of PCU is

   component INVTN1
      port( I, OEN : in std_logic;  ZN : out std_logic);
   end component;
   
   component OR2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component INR2D0
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component OAI211D0
      port( A1, A2, B, C : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component MUX2D1
      port( I0, I1, S : in std_logic;  Z : out std_logic);
   end component;
   
   component AOI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFCN1
      port( D, CP, CDN : in std_logic;  Q, QN : out std_logic);
   end component;
   
   component LH1
      port( E, D : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal IDR_7_port, IDR_3_port, IDB_4_port, IDB_0_port, n_574, IDB_2_port, 
      IDB_6_port, TDB_2_port, PC_2_port, TR_1_port, n_575, IDR_6_port, 
      IDR_5_port, TR_5_port, PC_6_port, TDB_6_port, TR_7_port, PC_4_port, 
      TDB_4_port, IDR_4_port, IDR_1_port, IDR_0_port, TDB_0_port, TR_3_port, 
      PC_0_port, TDB_1_port, TR_2_port, PC_1_port, n_579, TR_6_port, PC_5_port,
      TDB_5_port, n_clk1, n_577, n_589, IDR_2_port, TR_4_port, PC_7_port, 
      TDB_7_port, TDB_3_port, n_580, TR_0_port, PC_3_port, IDB_7_port, n_576, 
      n_581, IDB_3_port, n_578, IDB_1_port, IDB_5_port, n378, n392, n396, n397,
      n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, 
      n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, 
      n422, n423, n424, n425, n426, n427, n428, net168, net169, net170, net171,
      net172, net173, net174, net175, n429, n430, n431, n432, n433, n434, n435,
      n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, 
      n448, n449, n450, n451, n452 : std_logic;

begin
   PC <= ( PC_7_port, PC_6_port, PC_5_port, PC_4_port, PC_3_port, PC_2_port, 
      PC_1_port, PC_0_port );
   IDB <= ( IDB_7_port, IDB_6_port, IDB_5_port, IDB_4_port, IDB_3_port, 
      IDB_2_port, IDB_1_port, IDB_0_port );
   TDB <= ( TDB_7_port, TDB_6_port, TDB_5_port, TDB_4_port, TDB_3_port, 
      TDB_2_port, TDB_1_port, TDB_0_port );
   
   data_tri_6_label : INVTN1 port map( I => n396, OEN => C1, ZN => data(6));
   data_tri_3_label : INVTN1 port map( I => n402, OEN => C1, ZN => data(3));
   data_tri_4_label : INVTN1 port map( I => n399, OEN => C1, ZN => data(4));
   data_tri_0_label : INVTN1 port map( I => n398, OEN => C1, ZN => data(0));
   data_tri_5_label : INVTN1 port map( I => n400, OEN => C1, ZN => data(5));
   data_tri_1_label : INVTN1 port map( I => n401, OEN => C1, ZN => data(1));
   data_tri_2_label : INVTN1 port map( I => n397, OEN => C1, ZN => data(2));
   data_tri_7_label : INVTN1 port map( I => n403, OEN => C1, ZN => data(7));
   U168 : OR2D1 port map( A1 => error_in, A2 => C1, Z => n_589);
   U169 : INR2D0 port map( A1 => data(0), B1 => error_in, ZN => n_581);
   U170 : INR2D0 port map( A1 => data(1), B1 => error_in, ZN => n_580);
   U171 : INR2D0 port map( A1 => data(2), B1 => error_in, ZN => n_579);
   U172 : INR2D0 port map( A1 => data(3), B1 => error_in, ZN => n_578);
   U173 : INR2D0 port map( A1 => data(4), B1 => error_in, ZN => n_577);
   U174 : INR2D0 port map( A1 => data(5), B1 => error_in, ZN => n_576);
   U175 : INR2D0 port map( A1 => data(6), B1 => error_in, ZN => n_575);
   U176 : INR2D0 port map( A1 => data(7), B1 => error_in, ZN => n_574);
   U177 : INV0 port map( I => C5, ZN => n392);
   U178 : INV0 port map( I => S1, ZN => n378);
   U179 : OAI211D0 port map( A1 => n404, A2 => net175, B => n405, C => n406, ZN
                           => IDB_0_port);
   U180 : OAI211D0 port map( A1 => n404, A2 => net174, B => n407, C => n408, ZN
                           => IDB_1_port);
   U181 : OAI211D0 port map( A1 => n404, A2 => net173, B => n409, C => n410, ZN
                           => IDB_2_port);
   U182 : OAI211D0 port map( A1 => n404, A2 => net172, B => n411, C => n412, ZN
                           => IDB_3_port);
   U183 : OAI211D0 port map( A1 => n404, A2 => net171, B => n413, C => n414, ZN
                           => IDB_4_port);
   U184 : OAI211D0 port map( A1 => n404, A2 => net170, B => n415, C => n416, ZN
                           => IDB_5_port);
   U185 : OAI211D0 port map( A1 => n404, A2 => net169, B => n417, C => n418, ZN
                           => IDB_6_port);
   U186 : OAI211D0 port map( A1 => n404, A2 => net168, B => n419, C => n420, ZN
                           => IDB_7_port);
   U187 : INV0 port map( I => C6, ZN => n_clk1);
   U188 : NR2D0 port map( A1 => mux_sel(2), A2 => mux_sel(1), ZN => n421);
   U189 : AN2D1 port map( A1 => n421, A2 => n423, Z => n422);
   U190 : INV0 port map( I => mux_sel(1), ZN => n424);
   U191 : NR2D0 port map( A1 => n424, A2 => mux_sel(2), ZN => n425);
   U192 : AN2D1 port map( A1 => n425, A2 => n423, Z => n426);
   U193 : INV0 port map( I => mux_sel(0), ZN => n423);
   U194 : ND2D0 port map( A1 => mux_sel(0), A2 => n421, ZN => n404);
   U195 : AN2D1 port map( A1 => n425, A2 => mux_sel(0), Z => n427);
   U196 : AN3D1 port map( A1 => n423, A2 => n424, A3 => mux_sel(2), Z => n428);
   U197 : MUX2D1 port map( I0 => IDB_7_port, I1 => TDB_7_port, S => C1, Z => 
                           n429);
   U198 : MUX2D1 port map( I0 => IDB_6_port, I1 => TDB_6_port, S => C1, Z => 
                           n430);
   U199 : MUX2D1 port map( I0 => IDB_5_port, I1 => TDB_5_port, S => C1, Z => 
                           n431);
   U200 : MUX2D1 port map( I0 => IDB_4_port, I1 => TDB_4_port, S => C1, Z => 
                           n432);
   U201 : MUX2D1 port map( I0 => IDB_3_port, I1 => TDB_3_port, S => C1, Z => 
                           n433);
   U202 : MUX2D1 port map( I0 => IDB_2_port, I1 => TDB_2_port, S => C1, Z => 
                           n434);
   U203 : MUX2D1 port map( I0 => IDB_1_port, I1 => TDB_1_port, S => C1, Z => 
                           n435);
   U204 : MUX2D1 port map( I0 => IDB_0_port, I1 => TDB_0_port, S => C1, Z => 
                           n436);
   U205 : AOI22D0 port map( A1 => n422, A2 => IDR_7_port, B1 => TR_7_port, B2 
                           => n426, ZN => n419);
   U206 : AOI22D0 port map( A1 => ALU(7), A2 => n427, B1 => IXR(7), B2 => n428,
                           ZN => n420);
   U207 : AOI22D0 port map( A1 => n422, A2 => IDR_6_port, B1 => TR_6_port, B2 
                           => n426, ZN => n417);
   U208 : AOI22D0 port map( A1 => ALU(6), A2 => n427, B1 => IXR(6), B2 => n428,