cpug.vhd

debussy中文使用手册

                           n582, C1 => b(0), C2 => n583, ZN => n568);
   U113 : AOI222D0 port map( A1 => ARG207_2_port, A2 => n571, B1 => a(2), B2 =>
                           n584, C1 => b(2), C2 => n585, ZN => n569);
   U114 : XNR2D1 port map( A1 => b(7), A2 => a(7), ZN => n564);
   U115 : INV0 port map( I => sel(2), ZN => n586);
   U116 : AOI21D0 port map( A1 => sel(0), A2 => sel(1), B => n586, ZN => n587);
   U117 : AN3D1 port map( A1 => sel(0), A2 => n586, A3 => sel(1), Z => n588);
   U118 : AOI21D0 port map( A1 => sel(0), A2 => sel(1), B => sel(2), ZN => n571
                           );
   U119 : ND2D0 port map( A1 => sel(2), A2 => n570, ZN => n589);
   U120 : AN2D1 port map( A1 => b(7), A2 => a(7), Z => carry_port);
   U121 : AOI22D0 port map( A1 => ARG207_7_port, A2 => n571, B1 => carry_port, 
                           B2 => n588, ZN => n567);
   U122 : INV0 port map( I => n587, ZN => n565);
   U123 : INV0 port map( I => n570, ZN => X_cell_89_U4_Z_0);
   U124 : OAI21D0 port map( A1 => a(4), A2 => n565, B => n589, ZN => n572);
   U125 : OAI21D0 port map( A1 => b(5), A2 => n565, B => n589, ZN => n574);
   U126 : OAI21D0 port map( A1 => a(6), A2 => n565, B => n589, ZN => n576);
   U127 : OAI21D0 port map( A1 => b(3), A2 => n565, B => n589, ZN => n578);
   U128 : OAI21D0 port map( A1 => a(1), A2 => n565, B => n589, ZN => n580);
   U129 : IND2D1 port map( A1 => n589, B1 => a(7), ZN => n566);
   U130 : OAI21D0 port map( A1 => b(0), A2 => n565, B => n589, ZN => n582);
   U131 : OAI21D0 port map( A1 => b(2), A2 => n565, B => n589, ZN => n584);
   U132 : MUX2D1 port map( I0 => n587, I1 => n588, S => b(4), Z => n573);
   U133 : MUX2D1 port map( I0 => n587, I1 => n588, S => a(5), Z => n575);
   U134 : MUX2D1 port map( I0 => n587, I1 => n588, S => b(6), Z => n577);
   U135 : MUX2D1 port map( I0 => n587, I1 => n588, S => a(3), Z => n579);
   U136 : MUX2D1 port map( I0 => n587, I1 => n588, S => b(1), Z => n581);
   U137 : MUX2D1 port map( I0 => n587, I1 => n588, S => a(0), Z => n583);
   U138 : MUX2D1 port map( I0 => n587, I1 => n588, S => a(2), Z => n585);
   r71 : alulogic_DW01_addsub_8_1 port map( A(7) => a(7), A(6) => a(6), A(5) =>
                           a(5), A(4) => a(4), A(3) => a(3), A(2) => a(2), A(1)
                           => a(1), A(0) => a(0), B(7) => b(7), B(6) => b(6), 
                           B(5) => b(5), B(4) => b(4), B(3) => b(3), B(2) => 
                           b(2), B(1) => b(1), B(0) => b(0), CI => n591, 
                           ADD_SUB => X_cell_89_U4_Z_0, SUM(7) => 
                           X_return255_7_port, SUM(6) => X_return255_6_port, 
                           SUM(5) => X_return255_5_port, SUM(4) => 
                           X_return255_4_port, SUM(3) => X_return255_3_port, 
                           SUM(2) => X_return255_2_port, SUM(1) => 
                           X_return255_1_port, SUM(0) => X_return255_0_port, CO
                           => n592);
   r43 : alulogic_DW01_addsub_8_0 port map( A(7) => X_return255_7_port, A(6) =>
                           X_return255_6_port, A(5) => X_return255_5_port, A(4)
                           => X_return255_4_port, A(3) => X_return255_3_port, 
                           A(2) => X_return255_2_port, A(1) => 
                           X_return255_1_port, A(0) => X_return255_0_port, B(7)
                           => X_Logic0_port, B(6) => X_Logic0_port, B(5) => 
                           X_Logic0_port, B(4) => X_Logic0_port, B(3) => 
                           X_Logic0_port, B(2) => X_Logic0_port, B(1) => 
                           X_Logic0_port, B(0) => cin, CI => n590, ADD_SUB => 
                           sel(1), SUM(7) => ARG207_7_port, SUM(6) => 
                           ARG207_6_port, SUM(5) => ARG207_5_port, SUM(4) => 
                           ARG207_4_port, SUM(3) => ARG207_3_port, SUM(2) => 
                           ARG207_2_port, SUM(1) => ARG207_1_port, SUM(0) => 
                           ARG207_0_port, CO => n593);
   n590 <= '0';
   n591 <= '0';

end SYN_RTL;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity ALUB is

   port( IR : in std_logic_vector (1 downto 0);  IDB, PC : in std_logic_vector 
         (7 downto 0);  clock, reset : in std_logic;  S1 : buffer std_logic;  
         ALU, IXR : buffer std_logic_vector (7 downto 0);  bus_mode, alu_mode :
         in std_logic_vector (2 downto 0);  carry_mode : in std_logic;  
         error_out : out std_logic;  CH : in std_logic_vector (4 downto 0));

end ALUB;

architecture SYN_RTL of ALUB is

   component alulogic
      port( a, b : in std_logic_vector (7 downto 0);  cin : in std_logic;  sel 
            : in std_logic_vector (2 downto 0);  o : buffer std_logic_vector (7
            downto 0);  carry, zero : out std_logic);
   end component;
   
   component AN2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR3D1
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component OAI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INR2D0
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component MUX2D1
      port( I0, I1, S : in std_logic;  Z : out std_logic);
   end component;
   
   component XNR2D1
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFCN1Q
      port( D, CP, CDN : in std_logic;  Q : out std_logic);
   end component;
   
   signal X0_7_port, X0_6_port, X0_4_port, Carry0, ACC_1_port, T4, S1_port, 
      ACC_5_port, Zero0, ACC_7_port, T3, ACC_3_port, IXR_tmp_3_port, X0_2_port,
      X0_0_port, ALU_6_port, ACC_tmp_1_port, Y0_7_port, IXR_6_port, 
      IXR_tmp_7_port, ALU_2_port, Y0_3_port, T2, IXR_2_port, ALU_0_port, 
      Y0_1_port, ACC_tmp_5_port, ACC_tmp_7_port, IXR_0_port, IXR_tmp_5_port, 
      Y0_5_port, IXR_4_port, ACC_tmp_3_port, IXR_tmp_1_port, IXR_5_port, 
      Y0_4_port, ACC_tmp_2_port, X0_5_port, X0_3_port, ALU_1_port, Y0_0_port, 
      IXR_tmp_0_port, ACC_tmp_6_port, carry_flag, IXR_1_port, X0_1_port, 
      IXR_tmp_4_port, IXR_tmp_6_port, ALU_3_port, Y0_2_port, IXR_3_port, 
      ACC_tmp_4_port, IXR_tmp_2_port, ALU_7_port, n_707, ACC_tmp_0_port, 
      IXR_7_port, Y0_6_port, zero_flag, ACC_2_port, ACC_6_port, ACC_4_port, 
      ACC_0_port, n_708, n615, n616, n617, n618, n619, n620, n621, n622, n623, 
      n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, 
      n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, 
      n648, n649, n651, n652, n653, n654, n655, n656, n657, n658, n659 : 
      std_logic;

begin
   S1 <= S1_port;
   ALU <= ( ALU_7_port, ALU_6_port, n_707, n_708, ALU_3_port, ALU_2_port, 
      ALU_1_port, ALU_0_port );
   IXR <= ( IXR_7_port, IXR_6_port, IXR_5_port, IXR_4_port, IXR_3_port, 
      IXR_2_port, IXR_1_port, IXR_0_port );
   
   i_alulogic : alulogic port map( a(7) => X0_7_port, a(6) => X0_6_port, a(5) 
                           => X0_5_port, a(4) => X0_4_port, a(3) => X0_3_port, 
                           a(2) => X0_2_port, a(1) => X0_1_port, a(0) => 
                           X0_0_port, b(7) => Y0_7_port, b(6) => Y0_6_port, 
                           b(5) => Y0_5_port, b(4) => Y0_4_port, b(3) => 
                           Y0_3_port, b(2) => Y0_2_port, b(1) => Y0_1_port, 
                           b(0) => Y0_0_port, cin => carry_mode, sel(2) => 
                           alu_mode(2), sel(1) => alu_mode(1), sel(0) => 
                           alu_mode(0), o(7) => ALU_7_port, o(6) => ALU_6_port,
                           o(5) => n_707, o(4) => n_708, o(3) => ALU_3_port, 
                           o(2) => ALU_2_port, o(1) => ALU_1_port, o(0) => 
                           ALU_0_port, carry => Carry0, zero => Zero0);
   U233 : AN2D1 port map( A1 => n615, A2 => bus_mode(2), Z => n651);
   U234 : AN3D1 port map( A1 => bus_mode(2), A2 => n615, A3 => bus_mode(1), Z 
                           => n655);
   U235 : INV0 port map( I => bus_mode(0), ZN => n615);
   U236 : NR3D1 port map( A1 => bus_mode(0), A2 => bus_mode(2), A3 => n654, ZN 
                           => n656);
   U237 : NR3D1 port map( A1 => bus_mode(1), A2 => bus_mode(2), A3 => 
                           bus_mode(0), ZN => n657);
   U238 : ND2D0 port map( A1 => n616, A2 => n617, ZN => X0_7_port);
   U239 : ND2D0 port map( A1 => n618, A2 => n619, ZN => X0_6_port);
   U240 : ND2D0 port map( A1 => n620, A2 => n621, ZN => X0_5_port);
   U241 : ND2D0 port map( A1 => n622, A2 => n623, ZN => X0_4_port);
   U242 : ND2D0 port map( A1 => n624, A2 => n625, ZN => X0_3_port);
   U243 : ND2D0 port map( A1 => n626, A2 => n627, ZN => X0_2_port);
   U244 : ND2D0 port map( A1 => n628, A2 => n629, ZN => X0_1_port);
   U245 : ND2D0 port map( A1 => n630, A2 => n631, ZN => X0_0_port);
   U246 : OAI21D0 port map( A1 => n632, A2 => n633, B => n634, ZN => Y0_7_port)
                           ;
   U247 : OAI21D0 port map( A1 => n633, A2 => n635, B => n636, ZN => Y0_6_port)
                           ;
   U248 : OAI21D0 port map( A1 => n633, A2 => n637, B => n638, ZN => Y0_5_port)
                           ;
   U249 : OAI21D0 port map( A1 => n633, A2 => n639, B => n640, ZN => Y0_4_port)
                           ;
   U250 : OAI21D0 port map( A1 => n633, A2 => n641, B => n642, ZN => Y0_3_port)
                           ;
   U251 : OAI21D0 port map( A1 => n633, A2 => n643, B => n644, ZN => Y0_2_port)
                           ;
   U252 : OAI21D0 port map( A1 => n633, A2 => n645, B => n646, ZN => Y0_1_port)
                           ;
   U253 : OAI21D0 port map( A1 => n633, A2 => n647, B => n648, ZN => Y0_0_port)
                           ;
   U254 : AN2D1 port map( A1 => clock, A2 => CH(4), Z => T4);
   U255 : AN2D1 port map( A1 => CH(2), A2 => clock, Z => T2);
   U256 : OAI21D0 port map( A1 => CH(1), A2 => n649, B => CH(0), ZN => S1_port)
                           ;
   U257 : AN2D1 port map( A1 => CH(3), A2 => clock, Z => T3);
   error_out <= '0';
   U259 : OAI21D0 port map( A1 => n651, A2 => n653, B => n654, ZN => n652);
   U260 : INV0 port map( I => bus_mode(1), ZN => n654);
   U261 : INV0 port map( I => IXR_tmp_7_port, ZN => n632);
   U262 : ND3D0 port map( A1 => bus_mode(2), A2 => n654, A3 => bus_mode(0), ZN 
                           => n633);
   U263 : INV0 port map( I => IXR_tmp_6_port, ZN => n635);
   U264 : INV0 port map( I => IXR_tmp_5_port, ZN => n637);
   U265 : INV0 port map( I => IXR_tmp_4_port, ZN => n639);
   U266 : INV0 port map( I => IXR_tmp_3_port, ZN => n641);
   U267 : INV0 port map( I => IXR_tmp_2_port, ZN => n643);
   U268 : INV0 port map( I => IXR_tmp_1_port, ZN => n645);
   U269 : INV0 port map( I => IXR_tmp_0_port, ZN => n647);
   U270 : INR2D0 port map( A1 => bus_mode(0), B1 => bus_mode(2), ZN => n653);
   U271 : MUX2D1 port map( I0 => zero_flag, I1 => carry_flag, S => IR(0), Z => 
                           n658);
   U272 : XNR2D1 port map( A1 => IR(1), A2 => n658, ZN => n649);
   U273 : AOI22D0 port map( A1 => n659, A2 => PC(7), B1 => n655, B2 => 
                           ACC_tmp_7_port, ZN => n634);
   U274 : AOI22D0 port map( A1 => PC(6), A2 => n659, B1 => ACC_tmp_6_port, B2 
                           => n655, ZN => n636);
   U275 : AOI22D0 port map( A1 => PC(5), A2 => n659, B1 => ACC_tmp_5_port, B2 
                           => n655, ZN => n638);
   U276 : AOI22D0 port map( A1 => PC(4), A2 => n659, B1 => ACC_tmp_4_port, B2 
                           => n655, ZN => n640);
   U277 : AOI22D0 port map( A1 => PC(3), A2 => n659, B1 => ACC_tmp_3_port, B2 
                           => n655, ZN => n642);
   U278 : AOI22D0 port map( A1 => PC(2), A2 => n659, B1 => ACC_tmp_2_port, B2 
                           => n655, ZN => n644);
   U279 : AOI22D0 port map( A1 => PC(1), A2 => n659, B1 => ACC_tmp_1_port, B2 
                           => n655, ZN => n646);
   U280 : AOI22D0 port map( A1 => PC(0), A2 => n659, B1 => ACC_tmp_0_port, B2 
                           => n655, ZN => n648);
   U281 : AOI22D0 port map( A1 => IDB(7), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(7), ZN => n617);
   U282 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_7_port, B1 => n657, B2 =>
                           IXR_tmp_7_port, ZN => n616);
   U283 : AOI22D0 port map( A1 => IDB(6), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(6), ZN => n619);
   U284 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_6_port, B1 => n657, B2 =>
                           IXR_tmp_6_port, ZN => n618);
   U285 : AOI22D0 port map( A1 => IDB(5), A2 => bus_mode(2), B1 => n656, B2 => 
                           PC(5), ZN => n621);
   U286 : AOI22D0 port map( A1 => n653, A2 => ACC_tmp_5_port, B1 => n657, B2 =>
                           IXR_tmp_5_port, ZN => n620);
   U287 : AOI22D0 port map( A1 => IDB(4), A2 => bus_mode(2), B1 => n656, B2 =>