cpug.vhd

debussy中文使用手册

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_CPU is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_CPU;


library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity alulogic_DW01_addsub_8_1 is

   port( A, B : in std_logic_vector (7 downto 0);  CI, ADD_SUB : in std_logic; 
         SUM : out std_logic_vector (7 downto 0);  CO : out std_logic);

end alulogic_DW01_addsub_8_1;

architecture SYN_rpl of alulogic_DW01_addsub_8_1 is

   component XOR3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component XOR2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component FA1D1
      port( A, B, CI : in std_logic;  S, CO : out std_logic);
   end component;
   
   signal carry_4_port, B_AS_3_port, carry_2_port, B_AS_7_port, carry_6_port, 
      B_AS_5_port, B_AS_1_port, carry_7_port, carry_3_port, B_AS_0_port, 
      B_AS_4_port, B_AS_6_port, carry_5_port, carry_1_port, B_AS_2_port : 
      std_logic;

begin
   
   U1_7 : XOR3D1 port map( A1 => A(7), A2 => B_AS_7_port, A3 => carry_7_port, Z
                           => SUM(7));
   U4 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(7), Z => B_AS_7_port);
   U5 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(6), Z => B_AS_6_port);
   U6 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(5), Z => B_AS_5_port);
   U7 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(4), Z => B_AS_4_port);
   U8 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(3), Z => B_AS_3_port);
   U9 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(2), Z => B_AS_2_port);
   U10 : XOR2D1 port map( A1 => ADD_SUB, A2 => B(1), Z => B_AS_1_port);
   U11 : XOR2D1 port map( A1 => B(0), A2 => ADD_SUB, Z => B_AS_0_port);
   U1_1 : FA1D1 port map( A => A(1), B => B_AS_1_port, CI => carry_1_port, S =>
                           SUM(1), CO => carry_2_port);
   U1_0 : FA1D1 port map( A => A(0), B => B_AS_0_port, CI => ADD_SUB, S => 
                           SUM(0), CO => carry_1_port);
   U1_6 : FA1D1 port map( A => A(6), B => B_AS_6_port, CI => carry_6_port, S =>
                           SUM(6), CO => carry_7_port);
   U1_2 : FA1D1 port map( A => A(2), B => B_AS_2_port, CI => carry_2_port, S =>
                           SUM(2), CO => carry_3_port);
   U1_3 : FA1D1 port map( A => A(3), B => B_AS_3_port, CI => carry_3_port, S =>
                           SUM(3), CO => carry_4_port);
   U1_5 : FA1D1 port map( A => A(5), B => B_AS_5_port, CI => carry_5_port, S =>
                           SUM(5), CO => carry_6_port);
   U1_4 : FA1D1 port map( A => A(4), B => B_AS_4_port, CI => carry_4_port, S =>
                           SUM(4), CO => carry_5_port);

end SYN_rpl;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity alulogic_DW01_addsub_8_0 is

   port( A, B : in std_logic_vector (7 downto 0);  CI, ADD_SUB : in std_logic; 
         SUM : out std_logic_vector (7 downto 0);  CO : out std_logic);

end alulogic_DW01_addsub_8_0;

architecture SYN_rpl of alulogic_DW01_addsub_8_0 is

   component XOR3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component XOR2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component FA1D1
      port( A, B, CI : in std_logic;  S, CO : out std_logic);
   end component;
   
   signal carry_4_port, carry_2_port, carry_6_port, carry_7_port, carry_3_port,
      B_AS_0_port, carry_5_port, carry_1_port : std_logic;

begin
   
   U1_7 : XOR3D1 port map( A1 => A(7), A2 => ADD_SUB, A3 => carry_7_port, Z => 
                           SUM(7));
   U4 : XOR2D1 port map( A1 => B(0), A2 => ADD_SUB, Z => B_AS_0_port);
   U1_1 : FA1D1 port map( A => A(1), B => ADD_SUB, CI => carry_1_port, S => 
                           SUM(1), CO => carry_2_port);
   U1_0 : FA1D1 port map( A => A(0), B => B_AS_0_port, CI => ADD_SUB, S => 
                           SUM(0), CO => carry_1_port);
   U1_6 : FA1D1 port map( A => A(6), B => ADD_SUB, CI => carry_6_port, S => 
                           SUM(6), CO => carry_7_port);
   U1_2 : FA1D1 port map( A => A(2), B => ADD_SUB, CI => carry_2_port, S => 
                           SUM(2), CO => carry_3_port);
   U1_3 : FA1D1 port map( A => A(3), B => ADD_SUB, CI => carry_3_port, S => 
                           SUM(3), CO => carry_4_port);
   U1_5 : FA1D1 port map( A => A(5), B => ADD_SUB, CI => carry_5_port, S => 
                           SUM(5), CO => carry_6_port);
   U1_4 : FA1D1 port map( A => A(4), B => ADD_SUB, CI => carry_4_port, S => 
                           SUM(4), CO => carry_5_port);

end SYN_rpl;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_CPU.all;

entity alulogic is

   port( a, b : in std_logic_vector (7 downto 0);  cin : in std_logic;  sel : 
         in std_logic_vector (2 downto 0);  o : buffer std_logic_vector (7 
         downto 0);  carry, zero : out std_logic);

end alulogic;

architecture SYN_RTL of alulogic is

   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component OAI211D0
      port( A1, A2, B, C : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR8D1
      port( A1, A2, A3, A4, A5, A6, A7, A8 : in std_logic;  ZN : out std_logic
            );
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI222D0
      port( A1, A2, B1, B2, C1, C2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component XNR2D1
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component AOI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component OAI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component IND2D1
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component MUX2D1
      port( I0, I1, S : in std_logic;  Z : out std_logic);
   end component;
   
   component alulogic_DW01_addsub_8_1
      port( A, B : in std_logic_vector (7 downto 0);  CI, ADD_SUB : in 
            std_logic;  SUM : out std_logic_vector (7 downto 0);  CO : out 
            std_logic);
   end component;
   
   component alulogic_DW01_addsub_8_0
      port( A, B : in std_logic_vector (7 downto 0);  CI, ADD_SUB : in 
            std_logic;  SUM : out std_logic_vector (7 downto 0);  CO : out 
            std_logic);
   end component;
   
   signal X_return255_0_port, o_1_port, carry_port, o_5_port, 
      X_return255_4_port, o_7_port, X_return255_6_port, X_return255_2_port, 
      o_3_port, ARG207_4_port, ARG207_0_port, ARG207_2_port, ARG207_6_port, 
      ARG207_7_port, ARG207_3_port, ARG207_1_port, ARG207_5_port, o_2_port, 
      X_return255_3_port, X_Logic0_port, o_6_port, X_return255_7_port, o_4_port
      , X_return255_5_port, X_return255_1_port, o_0_port, n559, n560, n561, 
      n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, 
      n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, 
      n586, n587, n588, n589, X_cell_89_U4_Z_0, n590, n591, n592, n593 : 
      std_logic;

begin
   o <= ( o_7_port, o_6_port, o_5_port, o_4_port, o_3_port, o_2_port, o_1_port,
      o_0_port );
   carry <= carry_port;
   
   X_Logic0_port <= '0';
   U97 : INV0 port map( I => n559, ZN => o_4_port);
   U98 : INV0 port map( I => n560, ZN => o_5_port);
   U99 : INV0 port map( I => n561, ZN => o_6_port);
   U100 : INV0 port map( I => n562, ZN => o_3_port);
   U101 : INV0 port map( I => n563, ZN => o_1_port);
   U102 : OAI211D0 port map( A1 => n564, A2 => n565, B => n566, C => n567, ZN 
                           => o_7_port);
   U103 : INV0 port map( I => n568, ZN => o_0_port);
   U104 : INV0 port map( I => n569, ZN => o_2_port);
   U105 : NR8D1 port map( A1 => o_2_port, A2 => o_0_port, A3 => o_7_port, A4 =>
                           o_1_port, A5 => o_3_port, A6 => o_6_port, A7 => 
                           o_5_port, A8 => o_4_port, ZN => zero);
   U106 : NR2D0 port map( A1 => sel(1), A2 => sel(0), ZN => n570);
   U107 : AOI222D0 port map( A1 => ARG207_4_port, A2 => n571, B1 => b(4), B2 =>
                           n572, C1 => a(4), C2 => n573, ZN => n559);
   U108 : AOI222D0 port map( A1 => ARG207_5_port, A2 => n571, B1 => a(5), B2 =>
                           n574, C1 => b(5), C2 => n575, ZN => n560);
   U109 : AOI222D0 port map( A1 => ARG207_6_port, A2 => n571, B1 => b(6), B2 =>
                           n576, C1 => a(6), C2 => n577, ZN => n561);
   U110 : AOI222D0 port map( A1 => ARG207_3_port, A2 => n571, B1 => a(3), B2 =>
                           n578, C1 => b(3), C2 => n579, ZN => n562);
   U111 : AOI222D0 port map( A1 => ARG207_1_port, A2 => n571, B1 => b(1), B2 =>
                           n580, C1 => a(1), C2 => n581, ZN => n563);
   U112 : AOI222D0 port map( A1 => ARG207_0_port, A2 => n571, B1 => a(0), B2 =>