fsm_child2g.vhd

debussy中文使用手册

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_FSM_CHILD2 is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_FSM_CHILD2;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_FSM_CHILD2.all;

entity FSM_CHILD2 is

   port( Clock, Reset, TwoOnly, StartFSM2 : in std_logic;  Mux1_Sel, Mux2_Sel :
         out std_logic_vector (1 downto 0);  En_AB, En_AC, En_AD, En_BC, En_BD,
         En_CD : out std_logic);

end FSM_CHILD2;

architecture SYN_RTL of FSM_CHILD2 is

   component IND2D1
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component INR2D0
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN3D1
      port( A1, A2, A3 : in std_logic;  Z : out std_logic);
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI31D0
      port( A1, A2, A3, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFF1Q
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal Mux2_Sel_1_port, CurrStateFSM2202_2_port, CurrStateFSM2202_0_port, 
      CurrStateFSM2_0_port, Mux1_Sel_0_port, En_BD_port, Mux1_Sel_1_port, 
      En_BC_port, CurrStateFSM2_2_port, Mux2_Sel_0_port, En_AC_port, 
      CurrStateFSM2_1_port, CurrStateFSM2202_1_port, n224, n225, n226, n227, 
      n228, n229, n230, n231, n232, n233 : std_logic;

begin
   Mux1_Sel <= ( Mux1_Sel_1_port, Mux1_Sel_0_port );
   Mux2_Sel <= ( Mux2_Sel_1_port, Mux2_Sel_0_port );
   En_AC <= En_AC_port;
   En_BC <= En_BC_port;
   En_BD <= En_BD_port;
   En_CD <= Mux1_Sel_1_port;
   
   U91 : IND2D1 port map( A1 => En_BC_port, B1 => n224, ZN => Mux1_Sel_0_port);
   U92 : AOI21D0 port map( A1 => n226, A2 => CurrStateFSM2_2_port, B => n227, 
                           ZN => n225);
   U93 : AOI21D0 port map( A1 => n224, A2 => n228, B => Reset, ZN => 
                           CurrStateFSM2202_2_port);
   U94 : AOI21D0 port map( A1 => n229, A2 => n230, B => Reset, ZN => 
                           CurrStateFSM2202_1_port);
   U95 : AOI21D0 port map( A1 => n231, A2 => n229, B => Reset, ZN => 
                           CurrStateFSM2202_0_port);
   U96 : INR2D0 port map( A1 => n232, B1 => n226, ZN => En_AD);
   U97 : AN3D1 port map( A1 => StartFSM2, A2 => n226, A3 => n232, Z => En_AB);
   U98 : NR2D0 port map( A1 => n233, A2 => CurrStateFSM2_2_port, ZN => 
                           Mux2_Sel_0_port);
   U99 : NR2D0 port map( A1 => Mux2_Sel_0_port, A2 => CurrStateFSM2_2_port, ZN 
                           => n232);
   U100 : AN2D1 port map( A1 => Mux2_Sel_0_port, A2 => CurrStateFSM2_1_port, Z 
                           => En_BC_port);
   U101 : ND2D0 port map( A1 => Mux2_Sel_0_port, A2 => n226, ZN => n230);
   U102 : AOI21D0 port map( A1 => TwoOnly, A2 => En_AC_port, B => n227, ZN => 
                           n229);
   U103 : AOI31D0 port map( A1 => n226, A2 => n233, A3 => StartFSM2, B => 
                           En_BD_port, ZN => n231);
   U104 : ND3D0 port map( A1 => n226, A2 => n233, A3 => CurrStateFSM2_2_port, 
                           ZN => n224);
   U105 : AN3D1 port map( A1 => CurrStateFSM2_2_port, A2 => n226, A3 => 
                           CurrStateFSM2_0_port, Z => Mux1_Sel_1_port);
   U106 : NR3D0 port map( A1 => CurrStateFSM2_2_port, A2 => 
                           CurrStateFSM2_0_port, A3 => n226, ZN => n227);
   U107 : IND2D1 port map( A1 => TwoOnly, B1 => En_BC_port, ZN => n228);
   U108 : INV0 port map( I => CurrStateFSM2_0_port, ZN => n233);
   U109 : INV0 port map( I => CurrStateFSM2_1_port, ZN => n226);
   U110 : INV0 port map( I => n225, ZN => Mux2_Sel_1_port);
   U111 : INV0 port map( I => n230, ZN => En_AC_port);
   U112 : INV0 port map( I => n224, ZN => En_BD_port);
   CurrStateFSM2_reg_0_label : DFF1Q port map( D => CurrStateFSM2202_0_port, CP
                           => Clock, Q => CurrStateFSM2_0_port);
   CurrStateFSM2_reg_1_label : DFF1Q port map( D => CurrStateFSM2202_1_port, CP
                           => Clock, Q => CurrStateFSM2_1_port);
   CurrStateFSM2_reg_2_label : DFF1Q port map( D => CurrStateFSM2202_2_port, CP
                           => Clock, Q => CurrStateFSM2_2_port);

end SYN_RTL;