lib.vital

debussy中文使用手册

   VitalWireDelay (A2_ipd, A2, tipd_A2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((A2_ipd) AND (A1_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_ND2D0_VITAL of ND2D0 is
   for VITAL
   end for;
end CFG_ND2D0_VITAL;


---------------------------------------------------
----- CELL ND3D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity ND3D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.163 ns, 0.126 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.185 ns, 0.133 ns);
      tpd_A3_ZN                      :	VitalDelayType01 := (0.203 ns, 0.135 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      A3                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of ND3D0 : entity is TRUE;
end ND3D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of ND3D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (A3_ipd, A3, tipd_A3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, A3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((A2_ipd) AND (A1_ipd) AND (A3_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),
                 2 => (A3_ipd'last_event, tpd_A3_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_ND3D0_VITAL of ND3D0 is
   for VITAL
   end for;
end CFG_ND3D0_VITAL;


---------------------------------------------------
----- CELL ND4D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity ND4D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.170 ns, 0.152 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.193 ns, 0.168 ns);
      tpd_A3_ZN                      :	VitalDelayType01 := (0.212 ns, 0.180 ns);
      tpd_A4_ZN                      :	VitalDelayType01 := (0.228 ns, 0.184 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A4                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      A3                             :	in    STD_ULOGIC;
      A4                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of ND4D0 : entity is TRUE;
end ND4D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of ND4D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A3_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A4_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (A3_ipd, A3, tipd_A3);
   VitalWireDelay (A4_ipd, A4, tipd_A4);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, A3_ipd, A4_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((A2_ipd) AND (A1_ipd) AND (A3_ipd) AND (A4_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),
                 2 => (A3_ipd'last_event, tpd_A3_ZN, TRUE),
                 3 => (A4_ipd'last_event, tpd_A4_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_ND4D0_VITAL of ND4D0 is
   for VITAL
   end for;
end CFG_ND4D0_VITAL;


---------------------------------------------------
----- CELL NR2D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity NR2D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.191 ns, 0.167 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.178 ns, 0.146 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NR2D0 : entity is TRUE;
end NR2D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of NR2D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((A2_ipd) OR (A1_ipd)));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_NR2D0_VITAL of NR2D0 is
   for VITAL
   end for;
end CFG_NR2D0_VITAL;


---------------------------------------------------
----- CELL NR3D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity NR3D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.219 ns, 0.282 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.196 ns, 0.243 ns);
      tpd_A3_ZN                      :	VitalDelayType01 := (0.149 ns, 0.182 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      A3                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of NR3D0 : entity is TRUE;
end NR3D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of NR3D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (A3_ipd, A3, tipd_A3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, A3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((A2_ipd) OR (A1_ipd) OR (A3_ipd)));

      ----------------------
      --  Path Delay Section