lib.vital

debussy中文使用手册

---------------------------------------------------
----- CELL AN3D1 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity AN3D1 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_Z                       :	VitalDelayType01 := (0.262 ns, 0.316 ns);
      tpd_A2_Z                       :	VitalDelayType01 := (0.260 ns, 0.294 ns);
      tpd_A3_Z                       :	VitalDelayType01 := (0.253 ns, 0.268 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A3                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      A3                             :	in    STD_ULOGIC;
      Z                              :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AN3D1 : entity is TRUE;
end AN3D1;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of AN3D1 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A3_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (A3_ipd, A3, tipd_A3);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, A3_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS Z_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE Z_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      Z_zd := (A2_ipd) AND (A1_ipd) AND (A3_ipd);

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => Z,
       GlitchData => Z_GlitchData,
       OutSignalName => "Z",
       OutTemp => Z_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_Z, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_Z, TRUE),
                 2 => (A3_ipd'last_event, tpd_A3_Z, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AN3D1_VITAL of AN3D1 is
   for VITAL
   end for;
end CFG_AN3D1_VITAL;


---------------------------------------------------
----- CELL AOI21D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity AOI21D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.177 ns, 0.152 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.190 ns, 0.150 ns);
      tpd_B_ZN                       :	VitalDelayType01 := (0.169 ns, 0.255 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B                         :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      B                              :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AOI21D0 : entity is TRUE;
end AOI21D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of AOI21D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (B_ipd, B, tipd_B);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, B_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT ((B_ipd) OR ((A2_ipd) AND (A1_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),
                 2 => (B_ipd'last_event, tpd_B_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AOI21D0_VITAL of AOI21D0 is
   for VITAL
   end for;
end CFG_AOI21D0_VITAL;


---------------------------------------------------
----- CELL AOI222D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity AOI222D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.158 ns, 0.180 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.179 ns, 0.179 ns);
      tpd_B1_ZN                      :	VitalDelayType01 := (0.264 ns, 0.318 ns);
      tpd_B2_ZN                      :	VitalDelayType01 := (0.288 ns, 0.319 ns);
      tpd_C1_ZN                      :	VitalDelayType01 := (0.332 ns, 0.402 ns);
      tpd_C2_ZN                      :	VitalDelayType01 := (0.340 ns, 0.403 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_C2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      B1                             :	in    STD_ULOGIC;
      B2                             :	in    STD_ULOGIC;
      C1                             :	in    STD_ULOGIC;
      C2                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AOI222D0 : entity is TRUE;
end AOI222D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of AOI222D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL C2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   VitalWireDelay (B2_ipd, B2, tipd_B2);
   VitalWireDelay (C1_ipd, C1, tipd_C1);
   VitalWireDelay (C2_ipd, C2, tipd_C2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, B1_ipd, B2_ipd, C1_ipd, C2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd :=
       (NOT (((B2_ipd) AND (B1_ipd)) OR ((A2_ipd) AND (A1_ipd)) OR ((C2_ipd)
         AND (C1_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),
                 2 => (B1_ipd'last_event, tpd_B1_ZN, TRUE),
                 3 => (B2_ipd'last_event, tpd_B2_ZN, TRUE),
                 4 => (C1_ipd'last_event, tpd_C1_ZN, TRUE),
                 5 => (C2_ipd'last_event, tpd_C2_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AOI222D0_VITAL of AOI222D0 is
   for VITAL
   end for;
end CFG_AOI222D0_VITAL;


---------------------------------------------------
----- CELL AOI22D0 -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- synopsys translate_off
library IEEE;
use IEEE.VITAL_Timing.all;
-- synopsys translate_on


-- entity declaration --
entity AOI22D0 is
-- synopsys translate_off
   generic(
      TimingChecksOn: Boolean := True;
      InstancePath: STRING := "*";
      Xon: Boolean := True;
      MsgOn: Boolean := True;
      tpd_A1_ZN                      :	VitalDelayType01 := (0.194 ns, 0.154 ns);
      tpd_A2_ZN                      :	VitalDelayType01 := (0.217 ns, 0.152 ns);
      tpd_B1_ZN                      :	VitalDelayType01 := (0.263 ns, 0.210 ns);
      tpd_B2_ZN                      :	VitalDelayType01 := (0.285 ns, 0.211 ns);
      tipd_A1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_A2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B1                        :	VitalDelayType01 := (0.000 ns, 0.000 ns);
      tipd_B2                        :	VitalDelayType01 := (0.000 ns, 0.000 ns));

-- synopsys translate_on
   port(
      A1                             :	in    STD_ULOGIC;
      A2                             :	in    STD_ULOGIC;
      B1                             :	in    STD_ULOGIC;
      B2                             :	in    STD_ULOGIC;
      ZN                             :	out   STD_ULOGIC);
attribute VITAL_LEVEL0 of AOI22D0 : entity is TRUE;
end AOI22D0;

-- architecture body --
library IEEE;
use IEEE.VITAL_Primitives.all;
library VITAL;
use VITAL.VTABLES.all;
architecture VITAL of AOI22D0 is
   attribute VITAL_LEVEL1 of VITAL : architecture is TRUE;

   SIGNAL A1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL A2_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B1_ipd	 : STD_ULOGIC := 'X';
   SIGNAL B2_ipd	 : STD_ULOGIC := 'X';

begin

   ---------------------
   --  INPUT PATH DELAYs
   ---------------------
   WireDelay : block
   begin
   VitalWireDelay (A1_ipd, A1, tipd_A1);
   VitalWireDelay (A2_ipd, A2, tipd_A2);
   VitalWireDelay (B1_ipd, B1, tipd_B1);
   VitalWireDelay (B2_ipd, B2, tipd_B2);
   end block;
   --------------------
   --  BEHAVIOR SECTION
   --------------------
   VITALBehavior : process (A1_ipd, A2_ipd, B1_ipd, B2_ipd)


   -- functionality results
   VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
   ALIAS ZN_zd : STD_LOGIC is Results(1);

   -- output glitch detection variables
   VARIABLE ZN_GlitchData	: VitalGlitchDataType;

   begin

      -------------------------
      --  Functionality Section
      -------------------------
      ZN_zd := (NOT (((B2_ipd) AND (B1_ipd)) OR ((A2_ipd) AND (A1_ipd))));

      ----------------------
      --  Path Delay Section
      ----------------------
      VitalPathDelay01 (
       OutSignal => ZN,
       GlitchData => ZN_GlitchData,
       OutSignalName => "ZN",
       OutTemp => ZN_zd,
       Paths => (0 => (A1_ipd'last_event, tpd_A1_ZN, TRUE),
                 1 => (A2_ipd'last_event, tpd_A2_ZN, TRUE),
                 2 => (B1_ipd'last_event, tpd_B1_ZN, TRUE),
                 3 => (B2_ipd'last_event, tpd_B2_ZN, TRUE)),
       Mode => OnDetect,
       Xon => Xon,
       MsgOn => MsgOn,
       MsgSeverity => WARNING);

end process;

end VITAL;

configuration CFG_AOI22D0_VITAL of AOI22D0 is
   for VITAL
   end for;
end CFG_AOI22D0_VITAL;