fsm_child1g.vhd

debussy中文使用手册

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_FSM_CHILD1 is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_FSM_CHILD1;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_FSM_CHILD1.all;

entity FSM_CHILD1 is

   port( Clock, Reset, TwoOnly, StartFSM1 : in std_logic;  En_A, En_B, En_C, 
         En_D : out std_logic);

end FSM_CHILD1;

architecture SYN_RTL of FSM_CHILD1 is

   component OAI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR4D0
      port( A1, A2, A3, A4 : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND4D0
      port( A1, A2, A3, A4 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFF1Q
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal CurrStateFSM1113_1_port, CurrStateFSM1_1_port, En_C_port, En_D_port, 
      CurrStateFSM1_0_port, CurrStateFSM1113_0_port, En_B_port, n126, n127, 
      n128, n129, n130, n131, n132, n133 : std_logic;

begin
   En_B <= En_B_port;
   En_C <= En_C_port;
   En_D <= En_D_port;
   
   U51 : OAI21D0 port map( A1 => Reset, A2 => n126, B => n127, ZN => 
                           CurrStateFSM1113_1_port);
   U52 : ND2D0 port map( A1 => n127, A2 => n128, ZN => CurrStateFSM1113_0_port)
                           ;
   U53 : NR4D0 port map( A1 => n129, A2 => En_D_port, A3 => En_C_port, A4 => 
                           En_B_port, ZN => En_A);
   U54 : NR2D0 port map( A1 => n130, A2 => CurrStateFSM1_1_port, ZN => 
                           En_B_port);
   U55 : NR2D0 port map( A1 => n131, A2 => CurrStateFSM1_0_port, ZN => 
                           En_C_port);
   U56 : NR2D0 port map( A1 => n131, A2 => n130, ZN => En_D_port);
   U57 : ND3D0 port map( A1 => n132, A2 => n133, A3 => En_C_port, ZN => n127);
   U58 : ND4D0 port map( A1 => StartFSM1, A2 => n133, A3 => n130, A4 => n131, 
                           ZN => n128);
   U59 : INV0 port map( I => CurrStateFSM1_1_port, ZN => n131);
   U60 : INV0 port map( I => CurrStateFSM1_0_port, ZN => n130);
   U61 : INV0 port map( I => StartFSM1, ZN => n129);
   U62 : INV0 port map( I => Reset, ZN => n133);
   U63 : INV0 port map( I => TwoOnly, ZN => n132);
   U64 : INV0 port map( I => En_B_port, ZN => n126);
   CurrStateFSM1_reg_0_label : DFF1Q port map( D => CurrStateFSM1113_0_port, CP
                           => Clock, Q => CurrStateFSM1_0_port);
   CurrStateFSM1_reg_1_label : DFF1Q port map( D => CurrStateFSM1113_1_port, CP
                           => Clock, Q => CurrStateFSM1_1_port);

end SYN_RTL;