fsm_masterg.vhd

debussy中文使用手册

library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_FSM_MASTER is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_FSM_MASTER;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_FSM_MASTER.all;

entity FSM_MASTER is

   port( Clock, Reset, TwoOnly, FirstDataInRdy : in std_logic;  StartFSM1, 
         StartFSM2, StartFSM3, FirstDataOutRdy : out std_logic);

end FSM_MASTER;

architecture SYN_RTL of FSM_MASTER is

   component AOI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI31D0
      port( A1, A2, A3, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component NR2D0
      port( A1, A2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INV0
      port( I : in std_logic;  ZN : out std_logic);
   end component;
   
   component AN2D1
      port( A1, A2 : in std_logic;  Z : out std_logic);
   end component;
   
   component ND4D0
      port( A1, A2, A3, A4 : in std_logic;  ZN : out std_logic);
   end component;
   
   component ND3D0
      port( A1, A2, A3 : in std_logic;  ZN : out std_logic);
   end component;
   
   component INR2D0
      port( A1, B1 : in std_logic;  ZN : out std_logic);
   end component;
   
   component OAI21D0
      port( A1, A2, B : in std_logic;  ZN : out std_logic);
   end component;
   
   component AOI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component MOAI22D0
      port( A1, A2, B1, B2 : in std_logic;  ZN : out std_logic);
   end component;
   
   component DFF1Q
      port( D, CP : in std_logic;  Q : out std_logic);
   end component;
   
   signal StartFSM3_port, CurrStateMasterFSM_0_port, 
      CurrStateMasterFSM264_0_port, CurrStateMasterFSM264_2_port, 
      CurrStateMasterFSM_2_port, CurrStateMasterFSM_3_port, 
      CurrStateMasterFSM264_3_port, CurrStateMasterFSM264_1_port, 
      CurrStateMasterFSM_1_port, n288, n289, n290, n291, n292, n293, n294, n295
      , n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
      n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318 : 
      std_logic;

begin
   StartFSM3 <= StartFSM3_port;
   FirstDataOutRdy <= StartFSM3_port;
   
   U105 : AOI21D0 port map( A1 => n288, A2 => n289, B => n290, ZN => StartFSM1)
                           ;
   U106 : ND2D0 port map( A1 => n291, A2 => n292, ZN => StartFSM2);
   U107 : AOI31D0 port map( A1 => n293, A2 => n288, A3 => n294, B => Reset, ZN 
                           => CurrStateMasterFSM264_3_port);
   U108 : AOI21D0 port map( A1 => n295, A2 => n296, B => Reset, ZN => 
                           CurrStateMasterFSM264_2_port);
   U109 : AOI31D0 port map( A1 => n297, A2 => n296, A3 => n298, B => Reset, ZN 
                           => CurrStateMasterFSM264_1_port);
   U110 : AOI21D0 port map( A1 => n294, A2 => n299, B => Reset, ZN => 
                           CurrStateMasterFSM264_0_port);
   U111 : NR2D0 port map( A1 => n301, A2 => n302, ZN => n300);
   U112 : NR2D0 port map( A1 => FirstDataInRdy, A2 => CurrStateMasterFSM_1_port
                           , ZN => n303);
   U113 : AOI21D0 port map( A1 => n302, A2 => CurrStateMasterFSM_2_port, B => 
                           n305, ZN => n304);
   U114 : INV0 port map( I => CurrStateMasterFSM_3_port, ZN => n306);
   U115 : NR2D0 port map( A1 => n302, A2 => CurrStateMasterFSM_2_port, ZN => 
                           n305);
   U116 : NR2D0 port map( A1 => CurrStateMasterFSM_3_port, A2 => 
                           CurrStateMasterFSM_0_port, ZN => n307);
   U117 : AN2D1 port map( A1 => n291, A2 => n297, Z => n294);
   U118 : NR2D0 port map( A1 => CurrStateMasterFSM_1_port, A2 => 
                           CurrStateMasterFSM_2_port, ZN => n308);
   U119 : AOI31D0 port map( A1 => n309, A2 => n302, A3 => 
                           CurrStateMasterFSM_0_port, B => n310, ZN => n298);
   U120 : ND4D0 port map( A1 => TwoOnly, A2 => FirstDataInRdy, A3 => n308, A4 
                           => n307, ZN => n296);
   U121 : ND3D0 port map( A1 => CurrStateMasterFSM_3_port, A2 => n301, A3 => 
                           n311, ZN => n291);
   U122 : ND3D0 port map( A1 => CurrStateMasterFSM_3_port, A2 => n312, A3 => 
                           n305, ZN => n297);
   U123 : INR2D0 port map( A1 => n313, B1 => CurrStateMasterFSM_0_port, ZN => 
                           StartFSM3_port);
   U124 : ND4D0 port map( A1 => CurrStateMasterFSM_0_port, A2 => 
                           CurrStateMasterFSM_3_port, A3 => n301, A4 => n302, 
                           ZN => n288);
   U125 : ND2D0 port map( A1 => n307, A2 => n305, ZN => n292);
   U126 : ND2D0 port map( A1 => n307, A2 => n304, ZN => n289);
   U127 : ND4D0 port map( A1 => CurrStateMasterFSM_0_port, A2 => 
                           CurrStateMasterFSM_1_port, A3 => 
                           CurrStateMasterFSM_2_port, A4 => n306, ZN => n293);
   U128 : OAI21D0 port map( A1 => CurrStateMasterFSM_2_port, A2 => n290, B => 
                           CurrStateMasterFSM_3_port, ZN => n309);
   U129 : OAI21D0 port map( A1 => FirstDataInRdy, A2 => n314, B => n307, ZN => 
                           n299);
   U130 : AOI22D0 port map( A1 => CurrStateMasterFSM_0_port, A2 => n302, B1 => 
                           n312, B2 => CurrStateMasterFSM_1_port, ZN => n311);
   U131 : MOAI22D0 port map( A1 => n304, A2 => n306, B1 => n300, B2 => n306, ZN
                           => n313);
   U132 : MOAI22D0 port map( A1 => n302, A2 => CurrStateMasterFSM_3_port, B1 =>
                           n303, B2 => CurrStateMasterFSM_3_port, ZN => n315);
   U133 : ND2D0 port map( A1 => n306, A2 => n302, ZN => n316);
   U134 : ND2D0 port map( A1 => CurrStateMasterFSM_0_port, A2 => n315, ZN => 
                           n317);
   U135 : AOI22D0 port map( A1 => n316, A2 => CurrStateMasterFSM_2_port, B1 => 
                           n317, B2 => n301, ZN => n318);
   U136 : INV0 port map( I => FirstDataInRdy, ZN => n290);
   U137 : INV0 port map( I => CurrStateMasterFSM_0_port, ZN => n312);
   U138 : INV0 port map( I => CurrStateMasterFSM_1_port, ZN => n302);
   U139 : INV0 port map( I => CurrStateMasterFSM_2_port, ZN => n301);
   U140 : INV0 port map( I => n304, ZN => n314);
   U141 : INV0 port map( I => n292, ZN => n310);
   U142 : INV0 port map( I => n318, ZN => n295);
   CurrStateMasterFSM_reg_0_label : DFF1Q port map( D => 
                           CurrStateMasterFSM264_0_port, CP => Clock, Q => 
                           CurrStateMasterFSM_0_port);
   CurrStateMasterFSM_reg_1_label : DFF1Q port map( D => 
                           CurrStateMasterFSM264_1_port, CP => Clock, Q => 
                           CurrStateMasterFSM_1_port);
   CurrStateMasterFSM_reg_2_label : DFF1Q port map( D => 
                           CurrStateMasterFSM264_2_port, CP => Clock, Q => 
                           CurrStateMasterFSM_2_port);
   CurrStateMasterFSM_reg_3_label : DFF1Q port map( D => 
                           CurrStateMasterFSM264_3_port, CP => Clock, Q => 
                           CurrStateMasterFSM_3_port);

end SYN_RTL;