pram_mod.vhd

debussy中文使用手册

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: pram.v
--   description: This part modelize the program memory for the system operation

--                clock: system clock
--                VMA: valid memory address where read/write can be performed
--                R_W: memory read or memory write
--                addr: 8-bits address bus
--                data: 8-bits data bus


library IEEE;
use STD.STANDARD.all;
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
use work.packageCPU.all;

entity pram2 is
    port (
        clock : in std_logic;
        addr : in std_logic_vector(7 downto 0);
        VMA : in std_logic;
        R_W : in std_logic;
        dout : inout std_logic_vector(7 downto 0));
end pram2;

architecture behav of pram2 is
    type Mem_Type is array (0 to 2**addr'length-1)
                of std_logic_vector(dout'range);
    signal mem : Mem_Type;
---    signal addr_i      : integer :=0;
begin
  pram0: process(clock,VMA,R_W)

    FILE instuff : TEXT is IN "../memory_vhdl/pram.dat";

    variable Initialization : boolean := true;
    variable InLine         : line;
    variable memaddr        : integer := 0;
    variable Word           : bit_vector(dout'range);

  begin
    if Initialization then
      File_Read : while not Endfile(instuff) loop
        ReadLine(instuff, InLine);
        next File_Read when InLine'length = 0;        -- empty line

        read(InLine,Word);
        mem(memaddr) <= To_StdLogicVector(Word);
        memaddr := memaddr + 1;
      end loop File_Read;
      Initialization := false;
    end if;


    if VMA = '1' then
      if clock'event and
         clock'last_value = '0' and
         clock = '1' then
        if R_W = '1'  then -- Memory Read
             dout <= mem(to_natural(addr));
        else -- Memory Write
             mem(to_natural(addr)) <= dout;
        end if;
      end if;
    else
      dout <= (others => 'Z');
    end if;
  end process pram0;

end behav ;