child3.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************
 
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity FSM_CHILD3 is
   port (Clock, Reset, TwoOnly,StartFSM3: in std_logic;
	 Mux3_Sel: out std_logic_vector(1 downto 0));
end FSM_CHILD3;

architecture RTL of FSM_CHILD3 is 
   type   StateTypeFSM3 is (ST_Sum1, ST_Sum2,
                            ST_Sum3, ST_NoSum);
   signal CurrStateFSM3, NextStateFSM3: StateTypeFSM3;
begin
   --------
   -- FSM3
   --------
   FSM3_COMB: 
   process (StartFSM3, TwoOnly, CurrStateFSM3)
   begin
      Mux3_Sel <= "00";
      case (CurrStateFSM3) is
         when ST_Sum1  =>  Mux3_Sel <= "00";
                           if (StartFSM3 = '1') then
                              if (TwoOnly = '1') then
                                 NextStateFSM3 <= ST_NoSum;
                              else 
                                 NextStateFSM3 <= ST_Sum2;
                              end if;
                           else 
                              NextStateFSM3 <= ST_Sum1;
                           end if;
         when ST_Sum2  =>  Mux3_Sel <= "01";
                           NextStateFSM3 <= ST_Sum3;
         when ST_Sum3  =>  Mux3_Sel <= "10";
                           NextStateFSM3 <= ST_Sum1;
         when ST_NoSum =>  Mux3_Sel <= "11";
                           NextStateFSM3 <= ST_Sum1;
         when others   =>  NextStateFSM3 <= ST_Sum1;
      end case;
   end process FSM3_COMB;

   FSM3_SEQ: 
   process (Clock)
   begin
--      if rising_edge(Clock) then
        if (Clock'event and Clock = '1') then
         if (Reset = '1') then
            CurrStateFSM3 <= ST_Sum1;
         else
            CurrStateFSM3 <= NextStateFSM3;
         end if;
      end if;
   end process FSM3_SEQ;
end  RTL;