system.vhd

debussy中文使用手册

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-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
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-- *  of Novas Software Inc.                                              *
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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: system.vhd
--   description: This file is used to initalize the target system
--                and set up the stimulus for the simulation

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use work.my_pack.all;
entity system is
end system;

architecture Blk of system is

component FSM_MASTER
       port (Clock, Reset, TwoOnly, FirstDataInRdy:  in std_logic;
         StartFSM1, StartFSM2, StartFSM3: out std_logic;
         FirstDataOutRdy: out std_logic);
end component;
component FSM_CHILD1
	port (Clock, Reset, TwoOnly,StartFSM1:in std_logic;
          En_A, En_B, En_C, En_D: out std_logic);
end component;
component FSM_CHILD2
	 port (Clock, Reset, TwoOnly,StartFSM2: in std_logic;
         Mux1_Sel, Mux2_Sel:  out std_logic_vector(1 downto 0);
         En_AB, En_AC, En_AD,
         En_BC, En_BD, En_CD: out std_logic);
end component;
component FSM_CHILD3
	 port (Clock, Reset, TwoOnly,StartFSM3: in std_logic;
         Mux3_Sel: out std_logic_vector(1 downto 0));
end component;

component CPU
port (clock : in std_logic;
 reset : in std_logic;
 VMA : out std_logic;
 R_W : out std_logic;
 addr : out std_logic_vector(7 downto 0);
 data : inout std_logic_vector(7 downto 0));
end component;

component pram2
port (clock : in std_logic;
 addr : in std_logic_vector(7 downto 0);
 VMA : in std_logic;
 R_W : in std_logic;
 dout : inout std_logic_vector(7 downto 0));
end component;

   constant CYCLE : time := 50 ns;

   signal FSM_clock: std_logic := '0';
   signal FSM_reset: std_logic := '0';
   signal TwoOnly:std_logic:= '0'; 
   signal FirstDataInRdy: std_logic := '0';
   signal StartFSM1, StartFSM2, StartFSM3: std_logic;
   signal En_A, En_B, En_C, En_D: std_logic;
   signal Mux1_Sel, Mux2_Sel:  std_logic_vector(1 downto 0);
   signal En_AB, En_AC, En_AD: std_logic;
   signal En_BC, En_BD, En_CD:  std_logic;
   signal Mux3_Sel: std_logic_vector(1 downto 0);
   signal FirstDataOutRdy: std_logic;


  signal clock :std_logic :='0';
  signal reset :std_logic :='1';
  signal data   : std_logic_vector(7 downto 0);
  signal VMA    : std_logic;
  signal R_W    : std_logic;
  signal addr   : std_logic_vector(7 downto 0);

begin


FSM_MASTER_RTL: FSM_MASTER 
	 port map (FSM_clock, FSM_reset, TwoOnly, FirstDataInRdy,
                StartFSM1, StartFSM2, StartFSM3,FirstDataOutRdy);

FSM_CHILD1_RTL: FSM_CHILD1
	port map (FSM_clock, FSM_reset, TwoOnly,StartFSM1,
                En_A, En_B, En_C, En_D);

FSM_CHILD2_RTL: FSM_CHILD2
	port map (FSM_clock, FSM_reset, TwoOnly,StartFSM2,
                 Mux1_Sel, Mux2_Sel,
                 En_AB,En_AC,En_AD,En_BC,En_BD,En_CD);

FSM_CHILD3_RTL: FSM_CHILD3 
	port map (FSM_clock, FSM_reset,TwoOnly,StartFSM3,Mux3_Sel);

 i_CPU: CPU
 port map ( clock => clock , reset => reset , VMA => VMA
        , R_W => R_W , data => data , addr => addr);

 i_pram2: pram2
 port map ( clock => clock , addr => addr , VMA => VMA
        , R_W => R_W , dout => data);

FSM_clock <= not FSM_clock after  CYCLE ;
FirstDataInRdy <= '0', '1' after (5 * CYCLE);

 process
 begin 
   wait for 25 ns;
   FSM_reset <= '1';
   wait for 200 ns;
   FSM_reset <= '0';
   wait;
 end process;

 process
 begin
   wait for 25 ns;
   reset <='0';
   wait for 200 ns;
   reset <='1';
   wait ;
 end process;

 process
   variable flag : boolean := TRUE;
 begin
   wait for 250 ns;
   while flag loop
     clock <= '0';
     wait for 50 ns;
     clock <= '1';
     wait for 50 ns;
   end loop;
 end process;

end Blk;