ccu.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
-- *  All rights reserved                                                 *
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-- ************************************************************************

-- Debussy tutorial case: A simplified microprogramming-based CPU
-- file name: CCU.vhd
-- description: this part performs the arithmetic and login funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                C: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity CCU is
port ( TDB : in std_logic_vector(7 downto 0);
        clock : in std_logic;
        reset : in std_logic;
        CH : out std_logic_vector(4 downto 0);
        IR : out std_logic_vector(1 downto 0);
        alu_mode : out std_logic_vector(2 downto 0);
        bus_mode : out std_logic_vector(2 downto 0);
        carry_mode : out std_logic;
        mux_sel : out std_logic_vector(2 downto 0);
        C6 : out std_logic;
        C5 : out std_logic;
        C1 : out std_logic;
        C0 : out std_logic);
end CCU;

architecture RTL of CCU is
signal n_dout2  : std_logic_vector(1 downto 0);
signal rom_out  : std_logic_vector(7 downto 0);
signal MA  : std_logic_vector(7 downto 0);
signal n_C20  : std_logic;
signal n_C21  : std_logic;
signal mprom_out   : std_logic_vector(21 downto 0);
signal iclk   : std_logic;
signal IR7_IR2 : std_logic_vector(5 downto 0);
signal C21  : std_logic;
signal C20  : std_logic;
signal dout10   : std_logic_vector(17 downto 0);
signal C19     : std_logic;
signal IR_tmp : std_logic_vector(7 downto 0);
signal next_MA, i_dff30_nreg_l : std_logic_vector(7 downto 0);
signal i_dff30_clk_en   : std_logic;

component rom
port (addr : in std_logic_vector(5 downto 0);
 dout : out std_logic_vector(7 downto 0);
 addr_error : out std_logic);
end component;


component rom0
port (addr : in std_logic_vector(7 downto 0);
 dout : out std_logic_vector(21 downto 0);
 addr_error : out std_logic);
end component;


begin

 process (C19, reset)
 begin
 if (reset = '0') then
	IR <= "00";
	IR7_IR2 <= "000000";
-- elsif rising_edge(C19) then
  elsif (C19'event and C19 = '1') then
        IR <= TDB(1 downto 0);
        IR7_IR2 <= TDB(7 downto 2);
 end if;
 end process;

 i_rom: rom
 port map ( addr => IR7_IR2
        , dout => rom_out
        , addr_error => open
        );

 process (rom_out, next_MA, n_dout2)
 begin
        case n_dout2 is
        when "00" => MA <= (others => '0');
        when "01" => MA <= rom_out;
        when "10" => MA <= "00000000";
        when "11" => MA <= next_MA;
        when others => MA <= (others => 'X');
        end case;
 end process;




 n_dout2 <= n_C21 & n_C20;

 process (iclk, i_dff30_clk_en, reset)
 begin
 if (reset = '0') then
        next_MA <= "00000000";
-- elsif rising_edge(iclk) then
  elsif (iclk'event and iclk = '1') then
-- For Leapfrog       next_MA <= MA + '1';
       next_MA <= unsigned(MA) + '1';
 end if;
 end process;

 n_C20 <= C20 and reset;
 n_C21 <= reset and C21;

 i_rom0: rom0
 port map ( addr => MA
        , dout => mprom_out
        , addr_error => open
        );

 process (iclk, reset)
 begin
 if (reset = '0') then
 	C0 <= '0';
 	C1 <= '0';
 	mux_sel <= "000";
 	C5 <= '0';
 	C6 <= '0';
 	CH <= "00000";
 	alu_mode <= "000";
 	bus_mode <= "000";
 	carry_mode <= '0';
	C19 <= '0';
 	C20 <= '0';
 	C21 <= '0';

-- elsif rising_edge(iclk) then
  elsif (iclk'event and iclk = '1') then
 	C0 <= mprom_out(0);
 	C1 <= mprom_out(1);
 	mux_sel <= mprom_out(4 downto 2);
 	C5 <= mprom_out(5);
 	C6 <= mprom_out(6);
 	CH <= not(mprom_out(11 downto 7));
 	alu_mode <= mprom_out(14 downto 12);
 	bus_mode <= mprom_out(17 downto 15);
 	carry_mode <= mprom_out(18);
	C19 <= mprom_out(19);
 	C20 <= mprom_out(20);
 	C21 <= mprom_out(21);
 end if;
 end process;

 iclk <= not(clock);

end RTL;