master.vhd

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-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library work;

entity FSM_MASTER is
  port (Clock, Reset, TwoOnly, FirstDataInRdy:  in std_logic;
	 StartFSM1, StartFSM2, StartFSM3: out std_logic;
	FirstDataOutRdy: out std_logic);
end  FSM_MASTER;

architecture RTL of FSM_MASTER is 
   type   StateTypeMasterFSM is (ST0, ST1, ST2, ST3, ST4,
                                 ST5, ST6, ST7, ST8, ST9,
                                 ST10, ST11, ST12);
   signal CurrStateMasterFSM, 
          NextStateMasterFSM: StateTypeMasterFSM;
begin
   MASTER_FSM_COMB: 
   process (FirstDataInRdy,TwoOnly,CurrStateMasterFSM)
   begin
      StartFSM1 <= '0';
      StartFSM2 <= '0';
      StartFSM3 <= '0';
      FirstDataOutRdy <= '0';
      case (CurrStateMasterFSM) is
         when ST0  =>  if (FirstDataInRdy = '1') then
                          StartFSM1 <= '1';
                          if (TwoOnly = '1') then
                             NextStateMasterFSM <= ST7;
                          else 
                             NextStateMasterFSM <= ST1;
                          end if;
                       else 
                          NextStateMasterFSM <= ST0;
                       end if;
         when ST1  =>  NextStateMasterFSM <= ST2;
         when ST2  =>  StartFSM2 <= '1';
                       NextStateMasterFSM <= ST3;
         when ST3  =>  NextStateMasterFSM <= ST4;
         when ST4  =>  NextStateMasterFSM <= ST5;
         when ST5  =>  NextStateMasterFSM <= ST6;
         when ST6  =>  StartFSM3 <= '1';
                       FirstDataOutRdy <= '1';
                       if (FirstDataInRdy = '1') then
                          StartFSM1 <= '1';
                          NextStateMasterFSM <= ST1;
                       else 
                          NextStateMasterFSM <= ST0;
                       end if;
         when ST7  =>  NextStateMasterFSM <= ST8;
         when ST8  =>  StartFSM2 <= '1';
                       NextStateMasterFSM <= ST9;
         when ST9  =>  if (FirstDataInRdy = '1') then
                          StartFSM1 <= '1';
                          NextStateMasterFSM <= ST10;
                       else 
                          NextStateMasterFSM <= ST12;
                       end if;
         when ST10 =>  StartFSM3 <= '1';
                       FirstDataOutRdy <= '1';
                       NextStateMasterFSM <= ST11;
         when ST11 =>  StartFSM2 <= '1';
                       NextStateMasterFSM <= ST9;
         when ST12 =>  StartFSM3 <= '1';
                       FirstDataOutRdy <= '1';
                       NextStateMasterFSM <= ST0;
         when others =>  NextStateMasterFSM <= ST0;
      end case;
   end process MASTER_FSM_COMB;

   MASTER_FSM_SEQ: 
   process (Clock)
   begin
--      if rising_edge(Clock) then
        if (Clock'event and Clock = '1') then
         if (Reset = '1') then
            CurrStateMasterFSM <= ST0;
         else
            CurrStateMasterFSM <= NextStateMasterFSM;
         end if;
      end if;
   end process MASTER_FSM_SEQ;

end  RTL;