child1.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
entity FSM_CHILD1 is
    port (Clock, Reset, TwoOnly,StartFSM1:in std_logic;
	  En_A, En_B, En_C, En_D: out std_logic);

end FSM_CHILD1;
architecture RTL of FSM_CHILD1 is
   type   StateTypeFSM1 is (ST_A, ST_B, ST_C, ST_D);
   signal CurrStateFSM1, NextStateFSM1: StateTypeFSM1;
begin
   --------
   -- FSM1
   --------
   FSM1_COMB: 
   process (StartFSM1, TwoOnly, CurrStateFSM1)
   begin
      En_A <= '0';
      En_B <= '0';
      En_C <= '0';
      En_D <= '0';
      case (CurrStateFSM1) is
         when ST_A =>  if (StartFSM1 = '1') then
                          En_A <= '1';
                          NextStateFSM1 <= ST_B;
                       else 
                          NextStateFSM1 <= ST_A;
                       end if;
         when ST_B =>  En_B <= '1';
                       NextStateFSM1 <= ST_C;
         when ST_C =>  En_C <= '1';
                       if (TwoOnly = '1') then
                          NextStateFSM1 <= ST_A;
                       else 
                          NextStateFSM1 <= ST_D;
                       end if;
         when ST_D =>  En_D <= '1';
                       NextStateFSM1 <= ST_A;
         when others =>  NextStateFSM1 <= ST_A;
       end case;
   end process FSM1_COMB;

   FSM1_SEQ: 
   process (Clock)
   begin
--      if rising_edge(Clock) then
	if (Clock'event and Clock = '1') then
         if (Reset = '1') then
            CurrStateFSM1 <= ST_A;
         else
            CurrStateFSM1 <= NextStateFSM1;
         end if;
      end if;
   end process FSM1_SEQ;
end RTL;