child2.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity FSM_CHILD2 is
   port (Clock, Reset, TwoOnly,StartFSM2: in std_logic;
	 Mux1_Sel, Mux2_Sel:  out std_logic_vector(1 downto 0);
	 En_AB, En_AC, En_AD,
         En_BC, En_BD, En_CD: out std_logic);
end FSM_CHILD2;

architecture RTL of FSM_CHILD2 is 
   type   StateTypeFSM2 is (Zero, One, Two, Three, Four, Five);
   signal CurrStateFSM2, NextStateFSM2: StateTypeFSM2;
begin
   --------
   -- FSM2
   --------
   FSM2_COMB: 
   process (StartFSM2, TwoOnly, CurrStateFSM2)
   begin
      Mux1_Sel <= "00";
      Mux2_Sel <= "00";
      En_AB <= '0';
      En_AC <= '0';
      En_AD <= '0';
      En_BC <= '0';
      En_BD <= '0';
      En_CD <= '0';
      case (CurrStateFSM2) is
         when Zero  =>  Mux1_Sel <= "00";
                        Mux2_Sel <= "00";
                        if (StartFSM2 = '1') then
                           NextStateFSM2 <= One;
                           En_AB <= '1';
                        else 
                           NextStateFSM2 <= Zero;
                        end if;
         when One   =>  Mux1_Sel <= "00";
                        Mux2_Sel <= "01";
                        En_AC <= '1';
                        if (TwoOnly = '1') then
                           NextStateFSM2 <= Three;
                        else
                           NextStateFSM2 <= Two;
                        end if;
         when Two   =>  Mux1_Sel <= "00";
                        Mux2_Sel <= "10";
                        En_AD <= '1';
                        NextStateFSM2 <= Three;
         when Three =>  Mux1_Sel <= "01";
                        Mux2_Sel <= "01";
                        En_BC <= '1';
                        if (TwoOnly = '1') then
                           NextStateFSM2 <= Zero;
                        else
                           NextStateFSM2 <= Four;
                        end if;
         when Four  =>  Mux1_Sel <= "01";
                        Mux2_Sel <= "10";
                        En_BD <= '1';
                        NextStateFSM2 <= Five;
         when Five  =>  Mux1_Sel <= "10";
                        Mux2_Sel <= "10";
                        En_CD <= '1';
                        NextStateFSM2 <= Zero;
         when others =>  NextStateFSM2 <= Zero;
      end case;
   end process FSM2_COMB;

   FSM2_SEQ: 
   process (Clock)
   begin
--      if rising_edge(Clock) then
        if (Clock'event and Clock = '1') then
         if (Reset = '1') then
            CurrStateFSM2 <= Zero;
         else
            CurrStateFSM2 <= NextStateFSM2;
         end if;
      end if;
   end process FSM2_SEQ;
end RTL;