verilog.dump

debussy中文使用手册

$date
    Jul 26, 1997  13:37:48
$end
$version
    VERILOG-XL 2.3.3
$end
$timescale
     1ns
$end

$scope module system $end
$var wire      1 !    VMA  $end
$var wire      1 "    R_W  $end
$var parameter 32 #    CYCLE  $end
$var reg       1 $    clock  $end
$var reg       1 %    reset  $end
$var wire      8 &    addr [7:0] $end
$var wire      8 '    data [7:0] $end

$scope module i_cpu $end
$var wire      1 (    clock  $end
$var wire      1 )    reset  $end
$var wire      8 '    data [7:0] $end
$var reg       1 *    VMA  $end
$var reg       1 +    R_W  $end
$var parameter 32 ,    tHld  $end
$var parameter 32 -    ADDRSIZE  $end
$var parameter 32 .    WIDTH  $end
$var wire      8 /    data_in [7:0] $end
$var reg       8 0    acc [7:0] $end
$var reg       8 1    ir [7:0] $end
$var reg       8 2    index_reg [7:0] $end
$var reg       8 3    tmp_data [7:0] $end
$var reg       8 4    data_bus [7:0] $end
$var reg       9 5    result [8:0] $end
$var reg       8 6    pc [7:0] $end
$var reg       8 7    addr [7:0] $end
$var reg       8 8    tmp_addr [7:0] $end
$var reg       2 9    status_reg [1:0] $end
$var reg       2 :    test [1:0] $end

$scope task fetch_address $end
$upscope $end


$scope task fetch_operand $end
$upscope $end


$scope task write_mem $end
$upscope $end


$scope task set_status_reg $end
$upscope $end

$upscope $end


$scope module i_pram $end
$var wire      1 ;    clock  $end
$var wire      1 !    VMA  $end
$var wire      1 "    R_W  $end
$var wire      8 &    addr [7:0] $end
$var wire      8 '    data [7:0] $end
$var reg       8 <    dataout [7:0] $end
$upscope $end

$upscope $end

$enddefinitions $end
$dumpvars
x!
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b00000000000000000000000000110010 #
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b00000000000000000000000000000101 ,
b00000000000000000000000000001000 -
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bxxxxxxxx /
bxxxxxxxx 0
bxxxxxxxx 1
bxxxxxxxx 2
bxxxxxxxx 3
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bxxxxxxxx 6
bxxxxxxxx 7
bxxxxxxxx 8
bxx 9
bxx :
0;
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$end
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#12300
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