arithlogic_vhd.vhd

debussy中文使用手册

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--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: alu.v
--   description: this parts perform the arithmetic and login funtion
--                which is defined by mode select

--                a,b: operand data inputs
--                cin: carry input
--                sel: alu function select
--                dout: alu result data output
--                carry: alu result carry output
--                zero: alu result zero output


library IEEE;
use std.standard.all;
use std.textio.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use IEEE.std_logic_signed.all;
use work.packageCPU.all;
use work.functions.all;


entity arithlogic is
    port (
        a : in std_logic_vector(7 downto 0);
        b : in std_logic_vector(7 downto 0);
        cin : in std_logic;
        sel : in std_logic_vector(2 downto 0);
        alu_out : out std_logic_vector(7 downto 0);
        carry : out std_logic;
        zero : out std_logic);
end arithlogic;

architecture arithlogic of arithlogic is
    signal alu_tmp : std_logic_vector(7 downto 0);
begin
  process(a,b,cin,sel)
    variable a_var,b_var :bit_vector(7 downto 0);
    variable c_var :bit;
    variable result : bit_vector(8 downto 0);
    variable result1 : bit_vector(9 downto 0);
    variable one : bit_vector(8 downto 0) :="000000001";
  begin
    a_var := To_BitVector(a);
    b_var := To_BitVector(b);
    c_var := To_Bit(cin);
    case sel is
      when "000" =>
                result := a_var + b_var;
                if (c_var = '1') then
                    result1 := result + one;
                    result  := result1(8 downto 0);
                end if;
      when "001" => result := a_var - b_var;
                    result1 :=result - one;
                    result  :=result1(8 downto 0);
                if (c_var = '1') then
                    result1 := result + one;
                    result  := result1(8 downto 0);
                end if;
      when "010" => result := b_var - a_var;
                    result1 := result - one;
                    result := result1(8 downto 0);
                if (c_var = '1') then
                    result1 := result + one;
                    result  := result1(8 downto 0);
                end if;
      when "011" => result(7 downto 0) := a_var and b_var;
      when "100" => result(7 downto 0) := a_var or b_var;
      when "101" => result(7 downto 0) := a_var xor b_var;
      when "110" => result(7 downto 0) := a_var xor b_var;
                    result := not result;
      when others => result := (others => '0');
    end case;
    if (result(8) = '1') then
        carry <= '1';
    else
        carry <= '0';
    end if;
    alu_tmp <= To_StdLogicVector(result(7 downto 0)) after 1 ns;

    if ( is_zero(result(7 downto 0))) then
      zero <= '1' after 1 ns;
    else
      zero <= '0' after 1 ns;
    end if;
  end process;

  process (alu_tmp)
    begin
      alu_out <= alu_tmp;
  end process;

end arithlogic;