pcu.vhd

debussy中文使用手册

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-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
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-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
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-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997 Novas Software Inc.                                  *
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-- ************************************************************************

--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: ALUB.v
--   description: this part performs the arithmetic and login funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                C: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity PCU is
  port (
    mux_sel : in std_logic_vector(2 downto 0);
    C6 : in std_logic;
    C5 : in std_logic;
    C1 : in std_logic;
    ALU : in std_logic_vector(7 downto 0);
    S1 : in std_logic;
    IXR : in std_logic_vector(7 downto 0);
    reset : in std_logic;
    data : inout std_logic_vector(7 downto 0);
    PC : out std_logic_vector(7 downto 0);
    IDB : out std_logic_vector(7 downto 0);
    TDB : out std_logic_vector(7 downto 0);
    error_in : in std_logic
  );
end PCU;

architecture PCU of PCU is
signal n_din10  : std_logic_vector(7 downto 0);
signal n_dout1  : std_logic_vector(7 downto 0);
signal n_q0     : std_logic_vector(7 downto 0);
signal n_q2     : std_logic_vector(7 downto 0);
signal n_clk1   : std_logic;
signal TDB0     : std_logic_vector(7 downto 0);
signal clk_en1  : std_logic;
signal dout0    : std_logic;
signal dout01   : std_logic;
signal n_PC0    : std_logic_vector(7 downto 0);
signal i_dff_creg_l, i_dff_nreg_l : std_logic_vector(7 downto 0);
signal i_dff0_creg_l, i_dff0_nreg_l : std_logic_vector(7 downto 0);
signal i_dff1_creg_l, i_dff1_nreg_l : std_logic_vector(7 downto 0);


begin
  PC <= n_PC0;
 IDB <= n_dout1;
 TDB <= n_din10;
 clk_en1 <='1';


--Tri-state buffer
 process (C1)
 begin
        if (C1 = '1' or C1 = 'H') then
                data <= (others => 'Z');
        else
                data <= n_q0;
        end if;
 end process;


 process (n_q0, n_PC0, n_q2, ALU, IXR, mux_sel)
 begin
        case mux_sel is
        when "000"|"00L"|"0L0"|"0LL"|"L00"|"L0L"|"LL0"|"LLL" => n_dout1 <= n_q0;
        when "001"|"00H"|"0L1"|"0LH"|"L01"|"L0H"|"LL1"|"LLH" => n_dout1 <= n_PC0;
        when "010"|"01L"|"0H0"|"0HL"|"L10"|"L1L"|"LH0"|"LHL" => n_dout1 <= n_q2;
        when "011"|"01H"|"0H1"|"0HH"|"L11"|"L1H"|"LH1"|"LHH" => n_dout1 <= ALU;
        when "100"|"10L"|"1L0"|"1LL"|"H00"|"H0L"|"HL0"|"HLL" => n_dout1 <= IXR;
        when "101"|"10H"|"1L1"|"1LH"|"H01"|"H0H"|"HL1"|"HLH" => n_dout1 <= "00000000";
        when "110"|"11L"|"1H0"|"1HL"|"H10"|"H1L"|"HH0"|"HHL" => n_dout1 <= "00000000";
        when "111"|"11H"|"1H1"|"1HH"|"H11"|"H1H"|"HH1"|"HHH" => n_dout1 <= "00000000";
        when others => n_dout1 <= (others => 'X');
        end case;
 end process;

 process (n_dout1, n_din10, C1)
 begin
        case C1 is
        when '0'|'L' => TDB0 <= n_dout1 after 1 ns;
        when '1'|'H' => TDB0 <= n_din10 after 1 ns;
        when others => TDB0 <= (others => 'X') after 1 ns;
        end case;
 end process;


 process (C5, reset)
 begin
 if (reset ='0') then
        n_q0 <= "00000000";
 elsif (falling_edge(C5)) then
        n_q0 <= TDB0;
 end if;
 end process;

 process (S1, reset)
 begin
 if (reset ='0') then
        n_PC0 <= "00000000";
 elsif (falling_edge(S1)) then
        n_PC0 <= ALU;
 end if;
 end process;

 process (n_clk1, reset)
 begin
 if (reset ='0') then
        n_q2 <= "00000000";
 elsif (rising_edge(n_clk1)) then
        n_q2 <= ALU;
 end if;
 end process;

 n_clk1 <= not(C6);

 dout01 <= error_in and clk_en1;
 process (C1, dout01, data)
 begin
        if (dout01 = '1' or dout01 = 'H') then
                n_din10 <= "00000000";
        elsif (dout01 = '0' or dout01 = 'L') then
                if (C1 = '1' or C1 = 'H') then
                        n_din10 <= data;
                end if;
        else
                n_din10 <= (others => 'X');
        end if;
 end process;
end PCU;