ccu.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997 Novas Software Inc.                                  *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************

-- Debussy tutorial case: A simplified microprogramming-based CPU
-- file name: CCU.vhd
-- description: this part performs the arithmetic and login funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                C: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity CCU is
port ( TDB : in std_logic_vector(7 downto 0);
        clock : in std_logic;
        reset : in std_logic;
        CH : out std_logic_vector(4 downto 0);
        alu_mode : out std_logic_vector(2 downto 0);
        bus_mode : out std_logic_vector(2 downto 0);
        carry_mode : out std_logic;
        mux_sel : out std_logic_vector(2 downto 0);
        C6 : out std_logic;
        C5 : out std_logic;
        C1 : out std_logic;
        C0 : out std_logic;
        IR : out std_logic_vector(1 downto 0)
        );
end CCU;

architecture CCU of CCU is
signal n_q0     : std_logic_vector(7 downto 0);
signal n_dout2  : std_logic_vector(1 downto 0);
signal n_dout3  : std_logic_vector(7 downto 0);
signal n_dout4  : std_logic_vector(7 downto 0);
signal n_dout5  : std_logic_vector(7 downto 0);
signal n_q1     : std_logic_vector(7 downto 0);
signal din30    : std_logic_vector(7 downto 0);
signal n_dout0  : std_logic;
signal n_dout1  : std_logic;
signal n_din1   : std_logic_vector(21 downto 0);
signal clock0   : std_logic;
signal n_dout10 : std_logic_vector(5 downto 0);
signal n_q2     : std_logic_vector(21 downto 0);
signal n_din10  : std_logic;
signal n_din00  : std_logic;
signal dout10   : std_logic_vector(17 downto 0);
signal n_dout11 : std_logic_vector(3 downto 0);
signal clk0     : std_logic;
signal n_dout6  : std_logic;
signal i_dff3_creg_l, i_dff3_nreg_l : std_logic_vector(7 downto 0);
signal i_dff3_clk_en    : std_logic;
signal i_dff30_creg_l, i_dff30_nreg_l : std_logic_vector(7 downto 0);
signal i_dff30_clk_en   : std_logic;
signal i_dff300_creg_l, i_dff300_nreg_l : std_logic_vector(21 downto 0);

component maprom
port (addr : in std_logic_vector(5 downto 0);
 dout : out std_logic_vector(7 downto 0);
 addr_error : out std_logic);
end component;


component mprom
port (addr : in std_logic_vector(7 downto 0);
 dout : out std_logic_vector(21 downto 0);
 addr_error : out std_logic);
end component;


begin

 n_q0 <= i_dff3_creg_l;
 process (n_dout6, i_dff3_clk_en, i_dff3_nreg_l, reset)
 begin
 if (reset = '0' or reset = 'L') then
        i_dff3_creg_l <= "00000000";
 elsif (reset = '1' or reset = 'H') then
        if n_dout6'event and n_dout6 = '1' then
                if (i_dff3_clk_en = '1' or i_dff3_clk_en = 'H') then
                        i_dff3_creg_l <= i_dff3_nreg_l;
                end if;
        end if;
 else
        i_dff3_creg_l <= (others => 'X');
 end if;
 end process;

 i_dff3_nreg_l <= TDB;
 i_dff3_clk_en <= '1';
 IR <= n_q0(1 downto 0);
 n_dout10 <= n_q0(7 downto 2);

 i_maprom: maprom
 port map ( addr => n_dout10
        , dout => n_dout3
        , addr_error => open
        );

 process (din30, n_dout3, din30, n_q1, n_dout2)
 begin
        case n_dout2 is
        when "00"|"0L"|"L0"|"LL" => n_dout5 <= din30;
        when "01"|"0H"|"L1"|"LH" => n_dout5 <= n_dout3;
        when "10"|"1L"|"H0"|"HL" => n_dout5 <= din30;
        when "11"|"1H"|"H1"|"HH" => n_dout5 <= n_q1;
        when others => n_dout5 <= (others => 'X');
        end case;
 end process;


--Incrementor
 process (n_dout5)
 variable sum, t0 : std_logic_vector(8 downto 0);
 begin
        t0 := '0' & n_dout5;
        sum := unsigned(t0) + '1';
        -- sum := std_logic_vector(t0) + '1';
        n_dout4 <= sum(7 downto 0);
 end process;


 n_dout2 <= n_dout1 & n_dout0;

  n_q1 <= i_dff30_creg_l;
 process (clock0, i_dff30_clk_en, i_dff30_nreg_l, reset)
 begin
 if (reset = '0' or reset = 'L') then
        i_dff30_creg_l <= "00000000";
 elsif (reset = '1' or reset = 'H') then
        if clock0'event and clock0 = '1' then
             i_dff30_creg_l <= i_dff30_nreg_l;
        end if;
 else
        i_dff30_creg_l <= (others => 'X');
 end if;
 end process;

 i_dff30_nreg_l <= n_dout4;
-- Ground
 din30 <= (others => '0');
 n_dout0 <= n_din00 and reset;
 n_dout1 <= reset and n_din10;

 i_mprom: mprom
 port map ( addr => n_dout5
        , dout => n_din1
        , addr_error => open
        );

 n_q2 <= i_dff300_creg_l;
 process (clock0, reset)
 begin
 if (reset = '0' or reset = 'L') then
        i_dff300_creg_l <= "0000000000000000000000";
 elsif (reset = '1' or reset = 'H') then
        if rising_edge(clock0) then
             i_dff300_creg_l <= i_dff300_nreg_l;
        end if;
 else
        i_dff300_creg_l <= (others => 'X');
 end if;
 end process;
 i_dff300_nreg_l <= n_din1;

 clock0 <= not(clock);

 process (dout10)
 begin
        C0 <= dout10(0);
        C1 <= dout10(1);
        mux_sel <= dout10(4 downto 2);
        C5 <= dout10(5);
        C6 <= dout10(6);
        CH <= not(dout10(11 downto 7));
        alu_mode <= dout10(14 downto 12);
        bus_mode <= dout10(17 downto 15);
 end process;

 process (n_dout11)
 begin
        carry_mode <= n_dout11(0);
        clk0 <= n_dout11(1);
        n_din00 <= n_dout11(2);
        n_din10 <= n_dout11(3);
 end process;


 dout10 <= n_q2(17 downto 0);
 n_dout11 <= n_q2(21 downto 18);
 n_dout6 <= not(clk0);
end CCU;