cpu.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997 Novas Software Inc.                                  *
-- *  All rights reserved                                                 *
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-- ************************************************************************

-- Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: CPU.vhd
--   description: This part describes the top module of CPU including
--                CCU, PCU, ALU three block and their connectivity.

--                clock: system clock
--                reset: system reset
--                VMA: valid memory address where read/write can be performed
--                R_W: memory read or memory write
--                data: 8-bits data bus
--                addr: 8-bits address bus




library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity CPU is
port ( clock : in std_logic;
        reset : in std_logic;
        VMA : out std_logic;
        R_W : out std_logic;
        addr : out std_logic_vector(7 downto 0);
        data : inout std_logic_vector(7 downto 0));
end CPU;

architecture CPU of CPU is
signal n_CH0    : std_logic_vector(4 downto 0);
signal n_C60    : std_logic;
signal n_S10    : std_logic;
signal n_ALU0   : std_logic_vector(7 downto 0);
signal n_IXR0   : std_logic_vector(7 downto 0);
signal n_data0  : std_logic_vector(7 downto 0);
signal n_PC0    : std_logic_vector(7 downto 0);
signal n_reset0 : std_logic;
signal n_clock0 : std_logic;
signal n_IR0    : std_logic_vector(1 downto 0);
signal n_addr0  : std_logic_vector(7 downto 0);
signal n_TDB0   : std_logic_vector(7 downto 0);
signal n_alu_mode0      : std_logic_vector(2 downto 0);
signal n_bus_mode0      : std_logic_vector(2 downto 0);
signal n_carry_mode0    : std_logic;
signal n_mux_sel0       : std_logic_vector(2 downto 0);
signal n_C50    : std_logic;
signal n_C10    : std_logic;
signal n_error_out0     : std_logic;
signal n_C00    : std_logic;


component ALUB
port (IR : in std_logic_vector(1 downto 0);
 IDB : in std_logic_vector(7 downto 0);
 PC : in std_logic_vector(7 downto 0);
 CH :  std_logic_vector(4 downto 0);
 alu_mode : in std_logic_vector(2 downto 0);
 bus_mode : in std_logic_vector(2 downto 0);
 carry_mode : in std_logic;
 clock : in std_logic;
 reset : in std_logic;
 S1 : out std_logic;
 ALU : out std_logic_vector(7 downto 0);
 IXR : out std_logic_vector(7 downto 0);
 error_out : out std_logic);
end component;


component PCU
port (mux_sel : in std_logic_vector(2 downto 0);
 C6 : in std_logic;
 C5 : in std_logic;
 C1 : in std_logic;
 ALU : in std_logic_vector(7 downto 0);
 S1 : in std_logic;
 IXR : in std_logic_vector(7 downto 0);
 reset :  std_logic;
 data : inout std_logic_vector(7 downto 0);
 PC : out std_logic_vector(7 downto 0);
 IDB : out std_logic_vector(7 downto 0);
 TDB : out std_logic_vector(7 downto 0);
 error_in : in std_logic
 );
end component;


component CCU
port (TDB : in std_logic_vector(7 downto 0);
 clock : in std_logic;
 reset : in std_logic;
 CH : out std_logic_vector(4 downto 0);
 alu_mode : out std_logic_vector(2 downto 0);
 bus_mode : out std_logic_vector(2 downto 0);
 carry_mode : out std_logic;
 mux_sel : out std_logic_vector(2 downto 0);
 C6 : out std_logic;
 C5 : out std_logic;
 C1 : out std_logic;
 C0 : out std_logic;
 IR : out std_logic_vector(1 downto 0));
end component;


begin
 VMA <= n_C00;
 R_W <= n_C10;
 addr <= n_addr0;



 i_ALUB: ALUB
 port map ( IR => n_IR0
        , IDB => n_addr0
        , PC => n_PC0
        , CH => n_CH0
        , clock => clock
        , reset => reset
        , S1 => n_S10
        , ALU => n_ALU0
        , IXR => n_IXR0
        , alu_mode => n_alu_mode0
        , carry_mode => n_carry_mode0
        , bus_mode => n_bus_mode0
        , error_out => n_error_out0
        );

 i_PCU: PCU
 port map ( S1 => n_S10
        , ALU => n_ALU0
        , IXR => n_IXR0
        , reset => reset
        , PC => n_PC0
        , IDB => n_addr0
        , data => data
        , TDB => n_TDB0
        , error_in => n_error_out0
        , C6 => n_C60
        , C5 => n_C50
        , C1 => n_C10
        , mux_sel => n_mux_sel0
        );

 i_CCU: CCU
 port map ( TDB => n_TDB0
        , clock => clock
        , reset => reset
        , CH => n_CH0
        , IR => n_IR0
        , alu_mode => n_alu_mode0
        , bus_mode => n_bus_mode0
        , carry_mode => n_carry_mode0
        , mux_sel => n_mux_sel0
        , C6 => n_C60
        , C5 => n_C50
        , C1 => n_C10
        , C0 => n_C00
        );
end CPU;