system.vhd

来自「debussy中文使用手册」· VHDL 代码 · 共 127 行

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997 Novas Software Inc.                                  *
-- *  All rights reserved                                                 *
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-- ************************************************************************

--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: system.vhd
--   description: This file is used to initalize the target system
--                and set up the stimulus for the simulation

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-- use work.my_pack.all;
entity system is
end system;

architecture Blk of system is

component CPU
port (clock : in std_logic;
 reset : in std_logic;
 VMA : out std_logic;
 R_W : out std_logic;
 addr : out std_logic_vector(7 downto 0);
 data : inout std_logic_vector(7 downto 0));
end component;

component pram2
port (clock : in std_logic;
 addr : in std_logic_vector(7 downto 0);
 VMA : in std_logic;
 R_W : in std_logic;
 dout : inout std_logic_vector(7 downto 0));
end component;


  signal clock    : std_logic ; -- :='0';
  signal reset    : std_logic ;
  signal data     : std_logic_vector(7 downto 0);
  signal VMA      : std_logic;
  signal R_W      : std_logic;
  signal addr     : std_logic_vector(7 downto 0);
  signal ctl_data : std_logic :='0';
  signal ctl_rst0 : std_logic :='0';
  signal ctl_rst1 : std_logic :='1';
  signal rst0     : std_logic :='0';
  signal rst1     : std_logic :='1';

begin

 i_CPU: CPU
 port map ( clock => clock
        , reset => reset
        , VMA => VMA
        , R_W => R_W
        , data => data
        , addr => addr
        );

 i_pram: pram2
 port map ( clock => clock
        , addr => addr
        , VMA => VMA
        , R_W => R_W
        , dout => data
        );

 process
 begin
   wait for 25 ns;
   ctl_rst0 <='1';
   wait for 325 ns;
   ctl_rst0 <='0';
   wait ;
 end process;

 process
 begin
   wait for 50 ns;
   ctl_rst1 <= '0';
   wait for 300 ns;
   ctl_rst1 <='1';
   wait;
 end process;

 process (ctl_rst0)
 begin
    if(ctl_rst0 = '1') then
        reset <= rst0;
    else
	reset <= 'Z';
    end if;
 end process;

 process (ctl_rst1)
 begin
    if(ctl_rst1 = '1') then
        reset <= rst1;
    else
	reset <= 'Z';
    end if;
 end process;

 process
   variable flag : boolean := TRUE;
 begin
   wait for 250 ns;
   while flag loop
     clock <= '0';
     wait for 50 ns;
     clock <= '1';
     wait for 50 ns;
   end loop;
 end process;

end Blk;