alub.vhd

debussy中文使用手册

-- ************************************************************************
-- *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
-- *                                                                      *
-- *  This software contains information confidential and proprietary     *
-- *  to Novas Software Inc. It shall not be reproduced in whole          *
-- *  or in part or transferred to other documents, or disclosed          *
-- *  to third parties, or used for any purpose other than that           *
-- *  for which it was obtained, without the prior written consent        *
-- *  of Novas Software Inc.                                              *
-- *  (c) 1996, 1997 Novas Software Inc.                                  *
-- *  All rights reserved                                                 *
-- *                                                                      *
-- ************************************************************************

--   Debussy tutorial case: A simplified microprogramming-based CPU
--   file name: ALUB.v
--   description: this part performs the arithmetic and login funtion
--                on the operands of internal data bus(IDB)
--                IR: instruction register (from CCU)
--                IDB: internal data bus (from PCU)
--                PC: program counter (from PCU)
--                C: timing control (from CCU,12-bits)
--                clock: system clock
--                reset: system reset
--                S1: program counter control (to PCU)
--                ALU: ALU output data (to PCU)
--                IXR: index register (to PCU)


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity ALUB is
  port (
    IR : in std_logic_vector(1 downto 0);
    IDB : in std_logic_vector(7 downto 0);
    PC : in std_logic_vector(7 downto 0);
    CH : in std_logic_vector(4 downto 0);
    alu_mode : in std_logic_vector(2 downto 0);
    bus_mode : in std_logic_vector(2 downto 0);
    carry_mode : in std_logic;
    clock : in std_logic;
    reset : in std_logic;
    S1 : out std_logic;
    ALU : out std_logic_vector(7 downto 0);
    IXR : out std_logic_vector(7 downto 0);
    error_out : out std_logic

  );
end ALUB;

architecture ALUB of ALUB is
signal X0  : std_logic_vector(7 downto 0);
signal IXR_tmp     : std_logic_vector(7 downto 0);
signal ACC_tmp     : std_logic_vector(7 downto 0);
signal IXR0   : std_logic_vector(7 downto 0);
signal ACC   : std_logic_vector(7 downto 0);
signal zero_flag     : std_logic;
signal carry_flag  : std_logic;
signal S1_tmp    : std_logic;
signal T2 : std_logic;
signal T3   : std_logic;
signal T4   : std_logic;
signal ALU0     : std_logic_vector(7 downto 0);
signal Y0       : std_logic_vector(7 downto 0);
signal Carry0  : std_logic;
signal Zero0    : std_logic;
signal CH4   : std_logic;
signal CH3   : std_logic;
signal CH2  : std_logic;
signal CH1    : std_logic;
signal CH0    : std_logic;
signal n_din03  : std_logic_vector(7 downto 0);
signal n_eq0    : std_logic;
signal net_1  : std_logic;
signal net_2  : std_logic;
signal net_3  : std_logic;



component arithlogic
port (a : in std_logic_vector(7 downto 0);
 b : in std_logic_vector(7 downto 0);
 cin : in std_logic;
 sel : in std_logic_vector(2 downto 0);
 alu_out : out std_logic_vector(7 downto 0);
 carry : out std_logic;
 zero : out std_logic);
end component;


begin
 S1 <= S1_tmp;
 ALU <= ALU0;
 IXR <= IXR0;

 process (IXR_tmp, PC, ACC_tmp, IDB, bus_mode)
 begin
        case bus_mode is
        when "000"|"00L"|"0L0"|"0LL"|"L00"|"L0L"|"LL0"|"LLL" => X0 <= IXR_tmp;
        when "001"|"00H"|"0L1"|"0LH"|"L01"|"L0H"|"LL1"|"LLH" => X0 <= ACC_tmp;
        when "010"|"01L"|"0H0"|"0HL"|"L10"|"L1L"|"LH0"|"LHL" => X0 <= PC;
        when "011"|"01H"|"0H1"|"0HH"|"L11"|"L1H"|"LH1"|"LHH" => X0 <= ACC_tmp;
        when "100"|"10L"|"1L0"|"1LL"|"H00"|"H0L"|"HL0"|"HLL" => X0 <= IDB;
        when "101"|"10H"|"1L1"|"1LH"|"H01"|"H0H"|"HL1"|"HLH" => X0 <= IDB;
        when "110"|"11L"|"1H0"|"1HL"|"H10"|"H1L"|"HH0"|"HHL" => X0 <= IDB;
        when "111"|"11H"|"1H1"|"1HH"|"H11"|"H1H"|"HH1"|"HHH" => X0 <= IDB;
        when others => X0 <= (others => 'X');
        end case;
 end process;

 process (PC, IXR_tmp, ACC_tmp, bus_mode)
 begin
        case bus_mode is
        when "000"|"00L"|"0L0"|"0LL"|"L00"|"L0L"|"LL0"|"LLL" => Y0 <= "00000000";
        when "001"|"00H"|"0L1"|"0LH"|"L01"|"L0H"|"LL1"|"LLH" => Y0 <= PC;
        when "010"|"01L"|"0H0"|"0HL"|"L10"|"L1L"|"LH0"|"LHL" => Y0 <= "00000000";
        when "011"|"01H"|"0H1"|"0HH"|"L11"|"L1H"|"LH1"|"LHH" => Y0 <= "00000000";
        when "100"|"10L"|"1L0"|"1LL"|"H00"|"H0L"|"HL0"|"HLL" => Y0 <= PC;
        when "101"|"10H"|"1L1"|"1LH"|"H01"|"H0H"|"HL1"|"HLH" => Y0 <= IXR_tmp;
        when "110"|"11L"|"1H0"|"1HL"|"H10"|"H1L"|"HH0"|"HHL" => Y0 <= ACC_tmp;
        when "111"|"11H"|"1H1"|"1HH"|"H11"|"H1H"|"HH1"|"HHH" => Y0 <= "00000000";
        when others => Y0 <= (others => 'X');
        end case;
 end process;

 process (reset, T3)
 begin
 if (reset = '0' or reset = 'L') then
        IXR0 <= "00000000";
 elsif rising_edge(T3) then
        IXR0 <= ALU0;
 else
        IXR0 <= IXR0;
 end if;
 end process;


 process (reset, clock)
 begin
 if (reset = '0' or reset = 'L') then
        IXR_tmp <= "00000000";
 elsif rising_edge(clock) then
        IXR_tmp <= IXR0;
 else
        IXR_tmp <= IXR_tmp;
 end if;
 end process;

 process (reset, T4)
 begin
 if (reset = '0' or reset = 'L') then
        ACC <= "00000000";
 elsif rising_edge(T4) then
        ACC <= ALU0;
 else
        ACC <= ACC;
 end if;
 end process;

 process (reset, T2)
 begin
 if (reset = '0' or reset = 'L') then
        zero_flag <= '0';
 elsif  rising_edge(T2) then
        zero_flag <= Zero0;
 end if;
 end process;

 process (reset, clock)
 begin
 if (reset = '0' or reset = 'L') then
        ACC_tmp <= "00000000";
 -- elsif rising_edge(clock) then
 elsif falling_edge(clock) then
        ACC_tmp <= ACC;
 else
        ACC_tmp <= ACC_tmp;
 end if;
 end process;

 process (reset, T2)
 begin
 if (reset = '0' or reset = 'L') then
        carry_flag <= '0';
 elsif rising_edge(T2) then
        carry_flag <= Carry0;
 end if;
 end process;

 process (CH)
 begin
        CH0 <= CH(0);
        CH1 <= CH(1);
        CH2 <= CH(2);
        CH3 <= CH(3);
        CH4 <= CH(4);
 end process;

 process (zero_flag, carry_flag, IR(0))
 begin
        case IR(0) is
        when '0'|'L' => net_1 <= zero_flag;
        when '1'|'H' => net_1 <= carry_flag;
        when others => net_1 <= 'X';
        end case;
 end process;
 S1_tmp <= not(CH0) or (not(CH1) and (IR(1) xor net_1));
 T2 <= CH2 and clock;
 T4 <= clock and CH4;
 T3 <= clock and CH3;

 process (n_din03, ALU0)
 begin
        if (ALU0 = n_din03) then
                n_eq0 <= '1';
        else
                n_eq0 <= '0';
        end if;
 end process;

 n_din03 <= "00110000";
 net_3 <= IR(0) and S1_tmp;
 net_2 <= n_eq0 and not(CH1);
 error_out <= net_2 and net_3 and not(carry_flag) and zero_flag and net_1 ;

 i_alu: arithlogic
 port map ( a => X0
        , b => Y0
        , cin => carry_mode
        , sel => alu_mode
        , alu_out => ALU0
        , carry => Carry0
        , zero => Zero0
        );
end ALUB;