system.v

来自「debussy中文使用手册」· Verilog 代码 · 共 58 行

// ************************************************************************
// *  NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE                        *
// *                                                                      *
// *  This software contains information confidential and proprietary     *
// *  to Novas Software Inc. It shall not be reproduced in whole          *
// *  or in part or transferred to other documents, or disclosed          *
// *  to third parties, or used for any purpose other than that           *
// *  for which it was obtained, without the prior written consent        *
// *  of Novas Software Inc.                                              *
// *  (c) 1996, 1997, 1998 Novas Software Inc.                            *
// *  All rights reserved                                                 *
// *                                                                      *
// ************************************************************************
 
`timescale 1 ns / 1ns
module system;
parameter CYCLE = 50;

      reg Clock, Reset, ThreeOnly, FirstDataInRdy;
      wire       En_A, En_B, En_C, En_D;
      wire [1:0] Mux1_Sel, Mux2_Sel;
      wire       En_AB,En_AC,En_AD,En_BC,En_BD,En_CD;
      wire [1:0] Mux3_Sel;
      wire       FirstDataOutRdy;
      wire       StartFSM1, StartFSM2, StartFSM3;
initial
      begin
	 $fsdbDumpvars;
         #12500 $finish;
      end
initial
      begin
	Clock = 0;
	Reset = 0;
	FirstDataInRdy = 0;
	ThreeOnly = 0;
	#(5 * CYCLE)  FirstDataInRdy = 1;
      end
always
      begin
	forever #CYCLE Clock = ~Clock;
      end 
      
      fsm_master MASTER(Clock, Reset, ThreeOnly, FirstDataInRdy,
                StartFSM1, StartFSM2, StartFSM3,FirstDataOutRdy);

      fsm_child1 CHILD1(Clock, Reset, ThreeOnly,StartFSM1,
                En_A, En_B, En_C, En_D);

      fsm_child2 CHILD2(Clock, Reset, ThreeOnly,StartFSM2,
                 Mux1_Sel, Mux2_Sel,
                 En_AB,En_AC,En_AD,En_BC,En_BD,En_CD);

      fsm_child3 CHILD3(Clock, Reset, ThreeOnly,StartFSM3,Mux3_Sel);


endmodule