verilog.dump

debussy中文使用手册

$date
    Aug 14, 1997  17:28:33
$end
$version
    VERILOG-XL 2.5
$end
$timescale
     1ns
$end

$scope module system $end
$var wire      1 !    VMA  $end
$var wire      1 "    R_W  $end
$var parameter 32 #    CYCLE  $end
$var reg       1 $    clock  $end
$var reg       1 %    reset  $end
$var wire      1 &    addr [7] $end
$var wire      1 '    addr [6] $end
$var wire      1 (    addr [5] $end
$var wire      1 )    addr [4] $end
$var wire      1 *    addr [3] $end
$var wire      1 +    addr [2] $end
$var wire      1 ,    addr [1] $end
$var wire      1 -    addr [0] $end
$var wire      1 .    data [7] $end
$var wire      1 /    data [6] $end
$var wire      1 0    data [5] $end
$var wire      1 1    data [4] $end
$var wire      1 2    data [3] $end
$var wire      1 3    data [2] $end
$var wire      1 4    data [1] $end
$var wire      1 5    data [0] $end

$scope module i_cpu $end
$var wire      1 .    data [7] $end
$var wire      1 /    data [6] $end
$var wire      1 0    data [5] $end
$var wire      1 1    data [4] $end
$var wire      1 2    data [3] $end
$var wire      1 3    data [2] $end
$var wire      1 4    data [1] $end
$var wire      1 5    data [0] $end
$var wire      1 &    addr [7] $end
$var wire      1 '    addr [6] $end
$var wire      1 (    addr [5] $end
$var wire      1 )    addr [4] $end
$var wire      1 *    addr [3] $end
$var wire      1 +    addr [2] $end
$var wire      1 ,    addr [1] $end
$var wire      1 -    addr [0] $end
$var wire      1 6    clock  $end
$var wire      1 7    reset  $end
$var wire      1 !    VMA  $end
$var wire      1 "    R_W  $end
$var wire      1 8    S1  $end
$var wire      1 9    IR[0]  $end
$var wire      1 :    CH[2]  $end
$var wire      1 ;    alu_mode[1]  $end
$var wire      1 <    mux_sel[1]  $end
$var wire      1 =    ALU[6]  $end
$var wire      1 >    PC[2]  $end
$var wire      1 ?    TDB[2]  $end
$var wire      1 @    IXR[6]  $end
$var wire      1 A    ALU[2]  $end
$var wire      1 B    IXR[2]  $end
$var wire      1 C    bus_mode[1]  $end
$var wire      1 D    ALU[0]  $end
$var wire      1 E    IXR[0]  $end
$var wire      1 F    PC[6]  $end
$var wire      1 G    PC[4]  $end
$var wire      1 H    TDB[6]  $end
$var wire      1 I    TDB[4]  $end
$var wire      1 J    CH[4]  $end
$var wire      1 K    IR[1]  $end
$var wire      1 L    PC[1]  $end
$var wire      1 M    PC[0]  $end
$var wire      1 N    ALU[4]  $end
$var wire      1 O    IXR[4]  $end
$var wire      1 P    C6  $end
$var wire      1 Q    TDB[0]  $end
$var wire      1 R    CH[0]  $end
$var wire      1 S    carry_mode  $end
$var wire      1 T    ALU[5]  $end
$var wire      1 U    IXR[5]  $end
$var wire      1 V    error  $end
$var wire      1 W    TDB[1]  $end
$var wire      1 X    CH[1]  $end
$var wire      1 Y    ALU[1]  $end
$var wire      1 Z    mux_sel[2]  $end
$var wire      1 [    PC[5]  $end
$var wire      1 \    alu_mode[2]  $end
$var wire      1 ]    TDB[5]  $end
$var wire      1 ^    bus_mode[2]  $end
$var wire      1 _    IXR[1]  $end
$var wire      1 `    ALU[3]  $end
$var wire      1 a    bus_mode[0]  $end
$var wire      1 b    IXR[3]  $end
$var wire      1 c    PC[7]  $end
$var wire      1 d    TDB[7]  $end
$var wire      1 e    alu_mode[0]  $end
$var wire      1 f    ALU[7]  $end
$var wire      1 g    IXR[7]  $end
$var wire      1 h    mux_sel[0]  $end
$var wire      1 i    PC[3]  $end
$var wire      1 j    TDB[3]  $end
$var wire      1 k    CH[3]  $end
$var wire      1 l    C5  $end

$scope module i_ALUB $end
$var wire      1 K    IR [1] $end
$var wire      1 9    IR [0] $end
$var wire      1 c    PC [7] $end
$var wire      1 F    PC [6] $end
$var wire      1 [    PC [5] $end
$var wire      1 G    PC [4] $end
$var wire      1 i    PC [3] $end
$var wire      1 >    PC [2] $end
$var wire      1 L    PC [1] $end
$var wire      1 M    PC [0] $end
$var wire      1 ^    bus_mode [2] $end
$var wire      1 C    bus_mode [1] $end
$var wire      1 a    bus_mode [0] $end
$var wire      1 f    ALU [7] $end
$var wire      1 =    ALU [6] $end
$var wire      1 T    ALU [5] $end
$var wire      1 N    ALU [4] $end
$var wire      1 `    ALU [3] $end
$var wire      1 A    ALU [2] $end
$var wire      1 Y    ALU [1] $end
$var wire      1 D    ALU [0] $end
$var wire      1 g    IXR [7] $end
$var wire      1 @    IXR [6] $end
$var wire      1 U    IXR [5] $end
$var wire      1 O    IXR [4] $end
$var wire      1 b    IXR [3] $end
$var wire      1 B    IXR [2] $end
$var wire      1 _    IXR [1] $end
$var wire      1 E    IXR [0] $end
$var wire      1 &    IDB [7] $end
$var wire      1 '    IDB [6] $end
$var wire      1 (    IDB [5] $end
$var wire      1 )    IDB [4] $end
$var wire      1 *    IDB [3] $end
$var wire      1 +    IDB [2] $end
$var wire      1 ,    IDB [1] $end
$var wire      1 -    IDB [0] $end
$var wire      1 J    CH [4] $end
$var wire      1 k    CH [3] $end
$var wire      1 :    CH [2] $end
$var wire      1 X    CH [1] $end
$var wire      1 R    CH [0] $end
$var wire      1 \    alu_mode [2] $end
$var wire      1 ;    alu_mode [1] $end
$var wire      1 e    alu_mode [0] $end
$var wire      1 S    carry_mode  $end
$var wire      1 6    clock  $end
$var wire      1 7    reset  $end
$var wire      1 8    S1  $end
$var wire      1 V    error_out  $end
$var wire      1 m    X0[7]  $end
$var wire      1 n    X0[6]  $end
$var wire      1 o    X0[4]  $end
$var wire      1 p    carry  $end
$var wire      1 q    T4  $end
$var wire      1 r    ACC_tmp463[2]  $end
$var wire      1 s    zero  $end
$var wire      1 t    ACC_tmp463[6]  $end
$var wire      1 u    ACC_tmp463[4]  $end
$var wire      1 v    T3  $end
$var wire      1 w    ACC_tmp463[0]  $end
$var wire      1 x    IXR_tmp[3]  $end
$var wire      1 y    X0[2]  $end
$var wire      1 z    X0[0]  $end
$var wire      1 {    Y0[7]  $end
$var wire      1 |    ACC_tmp[1]  $end
$var wire      1 }    IXR_tmp[7]  $end
$var wire      1 ~    Y0[3]  $end
$var wire      1 !!   T2  $end
$var wire      1 "!   Y0[1]  $end
$var wire      1 #!   ACC_tmp[5]  $end
$var wire      1 $!   ACC_tmp[7]  $end
$var wire      1 %!   Y0[5]  $end
$var wire      1 &!   IXR_tmp[5]  $end
$var wire      1 '!   ACC_tmp[3]  $end
$var wire      1 (!   Y0[4]  $end
$var wire      1 )!   IXR_tmp[1]  $end
$var wire      1 *!   ACC_tmp[2]  $end
$var wire      1 +!   X0[5]  $end
$var wire      1 ,!   X0[3]  $end
$var wire      1 -!   Y0[0]  $end
$var wire      1 .!   IXR_tmp[0]  $end
$var wire      1 /!   carry_flag  $end
$var wire      1 0!   ACC_tmp[6]  $end
$var wire      1 1!   X0[1]  $end
$var wire      1 2!   IXR_tmp[4]  $end
$var wire      1 3!   IXR_tmp[6]  $end
$var wire      1 4!   Y0[2]  $end
$var wire      1 5!   ACC_tmp[4]  $end
$var wire      1 6!   IXR_tmp[2]  $end
$var wire      1 7!   Y0[6]  $end
$var wire      1 8!   ACC_tmp[0]  $end
$var wire      1 9!   zero_flag  $end
$var wire      1 :!   ACC_tmp463[1]  $end
$var wire      1 ;!   ACC_tmp463[5]  $end
$var wire      1 <!   ACC_tmp463[7]  $end
$var wire      1 =!   ACC_tmp463[3]  $end
$var wire      1 >!   n735  $end
$var wire      1 ?!   n736  $end
$var wire      1 @!   n737  $end
$var wire      1 A!   n738  $end
$var wire      1 B!   n739  $end
$var wire      1 C!   n740  $end
$var wire      1 D!   n741  $end
$var wire      1 E!   n742  $end
$var wire      1 F!   n743  $end
$var wire      1 G!   n744  $end
$var wire      1 H!   n745  $end
$var wire      1 I!   n746  $end
$var wire      1 J!   n747  $end
$var wire      1 K!   n748  $end
$var wire      1 L!   n749  $end
$var wire      1 M!   n750  $end
$var wire      1 N!   n751  $end
$var wire      1 O!   n752  $end
$var wire      1 P!   n753  $end
$var wire      1 Q!   n754  $end
$var wire      1 R!   n755  $end
$var wire      1 S!   n756  $end
$var wire      1 T!   n757  $end
$var wire      1 U!   n758  $end
$var wire      1 V!   n759  $end
$var wire      1 W!   n760  $end
$var wire      1 X!   n761  $end
$var wire      1 Y!   n762  $end
$var wire      1 Z!   n763  $end
$var wire      1 [!   n764  $end
$var wire      1 \!   n765  $end
$var wire      1 ]!   n766  $end
$var wire      1 ^!   n767  $end
$var wire      1 _!   n768  $end
$var wire      1 `!   n769  $end
$var wire      1 a!   n770  $end
$var wire      1 b!   n771  $end
$var wire      1 c!   n772  $end
$var wire      1 d!   n773  $end
$var wire      1 e!   n774  $end
$var wire      1 f!   n775  $end
$var wire      1 g!   n776  $end
$var wire      1 h!   n777  $end
$var wire      1 i!   n778  $end
$var wire      1 j!   n779  $end
$var wire      1 k!   n780  $end
$var wire      1 l!   n781  $end
$var wire      1 m!   n782  $end
$var wire      1 n!   n783  $end
$var wire      1 o!   n784  $end
$var wire      1 p!   n785  $end
$var wire      1 q!   n786  $end
$var wire      1 r!   n787  $end
$var wire      1 s!   n788  $end
$var wire      1 t!   n789  $end
$var wire      1 u!   n790  $end
$var wire      1 v!   n791  $end
$var wire      1 w!   n792  $end

$scope module i_alu $end
$var wire      1 m    a [7] $end
$var wire      1 n    a [6] $end
$var wire      1 +!   a [5] $end
$var wire      1 o    a [4] $end
$var wire      1 ,!   a [3] $end
$var wire      1 y    a [2] $end
$var wire      1 1!   a [1] $end
$var wire      1 z    a [0] $end
$var wire      1 \    select [2] $end
$var wire      1 ;    select [1] $end
$var wire      1 e    select [0] $end
$var wire      1 {    b [7] $end
$var wire      1 7!   b [6] $end
$var wire      1 %!   b [5] $end
$var wire      1 (!   b [4] $end
$var wire      1 ~    b [3] $end
$var wire      1 4!   b [2] $end
$var wire      1 "!   b [1] $end
$var wire      1 -!   b [0] $end
$var wire      1 f    out [7] $end
$var wire      1 =    out [6] $end
$var wire      1 T    out [5] $end
$var wire      1 N    out [4] $end
$var wire      1 `    out [3] $end
$var wire      1 A    out [2] $end
$var wire      1 Y    out [1] $end
$var wire      1 D    out [0] $end
$var wire      1 S    cin  $end
$var wire      1 p    carry  $end
$var wire      1 s    zero  $end
$var wire      1 x!   b320[9]  $end
$var wire      1 y!   n130[27]  $end
$var wire      1 z!   b320[4]  $end
$var wire      1 {!   b320[6]  $end
$var wire      1 |!   n130[25]  $end
$var wire      1 }!   b320[2]  $end
$var wire      1 ~!   n130[28]  $end
$var wire      1 !"   n130[31]  $end
$var wire      1 ""   b337[2]  $end
$var wire      1 #"   n142[25]  $end
$var wire      1 $"   n133[24]  $end
$var wire      1 %"   b303[7]  $end
$var wire      1 &"   n139[32]  $end
$var wire      1 '"   n136[25]  $end
$var wire      1 ("   n136[28]  $end
$var wire      1 )"   n136[31]  $end
$var wire      1 *"   n139[26]  $end
$var wire      1 +"   b337[6]  $end
$var wire      1 ,"   n133[29]  $end
$var wire      1 -"   n133[30]  $end
$var wire      1 ."   b303[3]  $end
$var wire      1 /"   n142[28]  $end
$var wire      1 0"   n142[31]  $end
$var wire      1 1"   n133[32]  $end
$var wire      1 2"   b303[1]  $end
$var wire      1 3"   n139[24]  $end
$var wire      1 4"   b337[4]  $end
$var wire      1 5"   b303[8]  $end
$var wire      1 6"   n139[29]  $end
$var wire      1 7"   n139[30]  $end
$var wire      1 8"   b337[9]  $end
$var wire      1 9"   n136[27]  $end
$var wire      1 :"   b303[5]  $end
$var wire      1 ;"   n133[26]  $end
$var wire      1 <"   n142[27]  $end
$var wire      1 ="   b337[8]  $end
$var wire      1 >"   n139[28]  $end
$var wire      1 ?"   n139[31]  $end
$var wire      1 @"   n136[26]  $end
$var wire      1 A"   b303[4]  $end
$var wire      1 B"   n142[26]  $end
$var wire      1 C"   n133[27]  $end
$var wire      1 D"   b337[1]  $end
$var wire      1 E"   n142[32]  $end
$var wire      1 F"   n136[32]  $end
$var wire      1 G"   b337[5]  $end
$var wire      1 H"   n139[25]  $end
$var wire      1 I"   b303[9]  $end
$var wire      1 J"   n136[29]  $end
$var wire      1 K"   n136[30]  $end
$var wire      1 L"   n139[27]  $end
$var wire      1 M"   b337[7]  $end
$var wire      1 N"   n133[28]  $end
$var wire      1 O"   n133[31]  $end
$var wire      1 P"   n142[30]  $end
$var wire      1 Q"   n142[29]  $end
$var wire      1 R"   b303[2]  $end
$var wire      1 S"   b337[3]  $end
$var wire      1 T"   n142[24]  $end
$var wire      1 U"   n133[25]  $end
$var wire      1 V"   b303[6]  $end
$var wire      1 W"   n136[24]  $end
$var wire      1 X"   b320[3]  $end
$var wire      1 Y"   n130[29]  $end
$var wire      1 Z"   n130[30]  $end
$var wire      1 ["   b320[7]  $end
$var wire      1 \"   n130[24]  $end
$var wire      1 ]"   n130[26]  $end
$var wire      1 ^"   b320[5]  $end
$var wire      1 _"   n130[32]  $end
$var wire      1 `"   b320[8]  $end
$var wire      1 a"   b320[1]  $end
$var wire      1 b"   n475  $end
$var wire      1 c"   n476  $end
$var wire      1 d"   n477  $end
$var wire      1 e"   n478  $end
$var wire      1 f"   n479  $end
$var wire      1 g"   n480  $end
$var wire      1 h"   n481  $end
$var wire      1 i"   n482  $end
$var wire      1 j"   n483  $end
$var wire      1 k"   n484  $end
$var wire      1 l"   n485  $end
$var wire      1 m"   n486  $end
$var wire      1 n"   n487  $end
$var wire      1 o"   n488  $end
$var wire      1 p"   n489  $end
$var wire      1 q"   n490  $end
$var wire      1 r"   n491  $end
$var wire      1 s"   n492  $end
$var wire      1 t"   n493  $end
$var wire      1 u"   n494  $end
$var wire      1 v"   n495  $end
$var wire      1 w"   n496  $end
$var wire      1 x"   n497  $end
$var wire      1 y"   n498  $end
$var wire      1 z"   n499  $end
$var wire      1 {"   n500  $end
$var wire      1 |"   n547  $end
$var wire      1 }"   n548  $end
$var wire      1 ~"   n549  $end
$var wire      1 !#   n550  $end
$var wire      1 "#   n551  $end
$var wire      1 ##   n552  $end
$var wire      1 $#   n553  $end
$var wire      1 %#   n554  $end
$var wire      1 &#   n555  $end
$var wire      1 '#   n556  $end
$var wire      1 (#   n557  $end
$var wire      1 )#   n558  $end
$var wire      1 *#   n559  $end
$var wire      1 +#   n560  $end
$var wire      1 ,#   n561  $end
$var wire      1 -#   n562  $end
$var wire      1 .#   n563  $end
$var wire      1 /#   n564  $end
$var wire      1 0#   n565  $end
$var wire      1 1#   n566  $end
$var wire      1 2#   n567  $end
$var wire      1 3#   n568  $end
$var wire      1 4#   n569  $end
$var wire      1 5#   n570  $end
$var wire      1 6#   n571  $end
$var wire      1 7#   n572  $end
$var wire      1 8#   n573  $end
$var wire      1 9#   n574  $end
$var wire      1 :#   n575  $end
$var wire      1 ;#   n576  $end
$var wire      1 <#   n577  $end
$var wire      1 =#   n578  $end
$var wire      1 >#   n579  $end
$var wire      1 ?#   n580  $end
$var wire      1 @#   n581  $end
$var wire      1 A#   n582  $end
$var wire      1 B#   n583  $end
$var wire      1 C#   n584  $end
$var wire      1 D#   n585  $end
$var wire      1 E#   n586  $end
$var wire      1 F#   n587  $end
$var wire      1 G#   n588  $end
$var wire      1 H#   n589  $end
$var wire      1 I#   n590  $end
$var wire      1 J#   n591  $end
$var wire      1 K#   n592  $end
$var wire      1 L#   n593  $end
$var wire      1 M#   n594  $end
$var wire      1 N#   n595  $end
$var wire      1 O#   n596  $end
$var wire      1 P#   n597  $end
$var wire      1 Q#   n598  $end
$var wire      1 R#   n599  $end
$var wire      1 S#   n600  $end
$var wire      1 T#   n601  $end
$var wire      1 U#   n602  $end

$scope module U98 $end
$var wire      1 ;    A  $end
$var wire      1 e    B  $end
$var wire      1 -#   C  $end
$var wire      1 /#   Z  $end
$upscope $end


$scope module U99 $end
$var wire      1 -#   A  $end
$var wire      1 0#   B  $end
$var wire      1 ;    C  $end
$var wire      1 )#   Z  $end
$upscope $end


$scope module U100 $end
$var wire      1 b"   A  $end
$var wire      1 c"   B  $end
$var wire      1 s    Z  $end
$upscope $end


$scope module U101 $end
$var wire      1 d"   A  $end
$var wire      1 e"   B  $end
$var wire      1 f"   C  $end
$var wire      1 g"   D  $end
$var wire      1 f    Z  $end
$upscope $end


$scope module U102 $end
$var wire      1 h"   A  $end
$var wire      1 i"   B  $end
$var wire      1 j"   C  $end
$var wire      1 k"   D  $end
$var wire      1 =    Z  $end
$upscope $end


$scope module U103 $end
$var wire      1 l"   A  $end
$var wire      1 m"   B  $end
$var wire      1 n"   C  $end
$var wire      1 o"   D  $end
$var wire      1 T    Z  $end
$upscope $end


$scope module U104 $end
$var wire      1 p"   A  $end
$var wire      1 q"   B  $end
$var wire      1 r"   C  $end
$var wire      1 s"   D  $end
$var wire      1 N    Z  $end
$upscope $end


$scope module U105 $end
$var wire      1 t"   A  $end
$var wire      1 u"   B  $end
$var wire      1 v"   C  $end
$var wire      1 w"   D  $end
$var wire      1 `    Z  $end
$upscope $end


$scope module U106 $end
$var wire      1 x"   A  $end
$var wire      1 y"   B  $end
$var wire      1 z"   C  $end
$var wire      1 {"   D  $end
$var wire      1 A    Z  $end
$upscope $end


$scope module U107 $end
$var wire      1 |"   A  $end
$var wire      1 }"   B  $end
$var wire      1 ~"   C  $end
$var wire      1 !#   D  $end
$var wire      1 Y    Z  $end
$upscope $end


$scope module U108 $end
$var wire      1 "#   A  $end
$var wire      1 ##   B  $end
$var wire      1 $#   C  $end
$var wire      1 %#   D  $end
$var wire      1 D    Z  $end
$upscope $end


$scope module U109 $end
$var wire      1 `"   A  $end
$var wire      1 &#   B  $end
$var wire      1 f"   Z  $end
$upscope $end


$scope module U110 $end
$var wire      1 ="   A  $end
$var wire      1 '#   B  $end
$var wire      1 d"   Z  $end
$upscope $end


$scope module U111 $end
$var wire      1 ["   A  $end
$var wire      1 &#   B  $end
$var wire      1 j"   Z  $end
$upscope $end


$scope module U112 $end
$var wire      1 M"   A  $end