cpu.vg

debussy中文使用手册

         );
    FD2 \IXR_tmp_reg[3]  ( .D(IXR[3]), .CP(n792), .CD(reset), .Q(\IXR_tmp[3] )
         );
    FD2 \IXR_tmp_reg[2]  ( .D(IXR[2]), .CP(n792), .CD(reset), .Q(\IXR_tmp[2] )
         );
    FD2 \IXR_tmp_reg[1]  ( .D(IXR[1]), .CP(n792), .CD(reset), .Q(\IXR_tmp[1] )
         );
    FD2 \IXR_tmp_reg[0]  ( .D(IXR[0]), .CP(n792), .CD(reset), .Q(\IXR_tmp[0] )
         );
    FD2 \ACC_tmp_reg[7]  ( .D(\ACC_tmp463[7] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[7] ) );
    FD2 \ACC_tmp_reg[6]  ( .D(\ACC_tmp463[6] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[6] ) );
    FD2 \ACC_tmp_reg[5]  ( .D(\ACC_tmp463[5] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[5] ) );
    FD2 \ACC_tmp_reg[4]  ( .D(\ACC_tmp463[4] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[4] ) );
    FD2 \ACC_tmp_reg[3]  ( .D(\ACC_tmp463[3] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[3] ) );
    FD2 \ACC_tmp_reg[2]  ( .D(\ACC_tmp463[2] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[2] ) );
    FD2 \ACC_tmp_reg[1]  ( .D(\ACC_tmp463[1] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[1] ) );
    FD2 \ACC_tmp_reg[0]  ( .D(\ACC_tmp463[0] ), .CP(n792), .CD(reset), .Q(
        \ACC_tmp[0] ) );
    FD2 \IXR_reg[7]  ( .D(ALU[7]), .CP(T3), .CD(reset), .Q(IXR[7]) );
    FD2 \IXR_reg[6]  ( .D(ALU[6]), .CP(T3), .CD(reset), .Q(IXR[6]) );
    FD2 \IXR_reg[5]  ( .D(ALU[5]), .CP(T3), .CD(reset), .Q(IXR[5]) );
    FD2 \IXR_reg[4]  ( .D(ALU[4]), .CP(T3), .CD(reset), .Q(IXR[4]) );
    FD2 \IXR_reg[3]  ( .D(ALU[3]), .CP(T3), .CD(reset), .Q(IXR[3]) );
    FD2 \IXR_reg[2]  ( .D(ALU[2]), .CP(T3), .CD(reset), .Q(IXR[2]) );
    FD2 \IXR_reg[1]  ( .D(ALU[1]), .CP(T3), .CD(reset), .Q(IXR[1]) );
    FD2 \IXR_reg[0]  ( .D(ALU[0]), .CP(T3), .CD(reset), .Q(IXR[0]) );
    FD2 \ACC_reg[7]  ( .D(ALU[7]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[7] ) );
    FD2 \ACC_reg[6]  ( .D(ALU[6]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[6] ) );
    FD2 \ACC_reg[5]  ( .D(ALU[5]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[5] ) );
    FD2 \ACC_reg[4]  ( .D(ALU[4]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[4] ) );
    FD2 \ACC_reg[3]  ( .D(ALU[3]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[3] ) );
    FD2 \ACC_reg[2]  ( .D(ALU[2]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[2] ) );
    FD2 \ACC_reg[1]  ( .D(ALU[1]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[1] ) );
    FD2 \ACC_reg[0]  ( .D(ALU[0]), .CP(T4), .CD(reset), .Q(\ACC_tmp463[0] ) );
    FD2 zero_flag_reg ( .D(zero), .CP(T2), .CD(reset), .Q(zero_flag) );
    FD2 carry_flag_reg ( .D(carry), .CP(T2), .CD(reset), .Q(carry_flag) );
endmodule


module CCU_DW01_inc_8_0 ( A, SUM );
input  [7:0] A;
output [7:0] SUM;
    wire \carry[4] , \carry[6] , \carry[2] , \carry[7] , \carry[3] , 
        \carry[5] ;
    IV U3 ( .A(A[0]), .Z(SUM[0]) );
    HA1 U1_1 ( .A(A[1]), .B(A[0]), .S(SUM[1]), .CO(\carry[2] ) );
    HA1 U1_6 ( .A(A[6]), .B(\carry[6] ), .S(SUM[6]), .CO(\carry[7] ) );
    HA1 U1_2 ( .A(A[2]), .B(\carry[2] ), .S(SUM[2]), .CO(\carry[3] ) );
    HA1 U1_7 ( .A(A[7]), .B(\carry[7] ), .S(SUM[7]) );
    HA1 U1_3 ( .A(A[3]), .B(\carry[3] ), .S(SUM[3]), .CO(\carry[4] ) );
    HA1 U1_4 ( .A(A[4]), .B(\carry[4] ), .S(SUM[4]), .CO(\carry[5] ) );
    HA1 U1_5 ( .A(A[5]), .B(\carry[5] ), .S(SUM[5]), .CO(\carry[6] ) );
endmodule


module CCU ( TDB, clock, reset, CH, alu_mode, bus_mode, carry_mode, mux_sel, 
    C6, C5, C1, C0, IR );
input  [7:0] TDB;
output [4:0] CH;
output [2:0] alu_mode;
output [2:0] bus_mode;
output [2:0] mux_sel;
output [1:0] IR;
input  clock, reset;
output carry_mode, C6, C5, C1, C0;
    wire \next_MA[3] , \CH391[2] , \MA182[0] , \MA[5] , \next_MA[7] , 
        \next_MA[5] , C21, \MA[7] , \CH391[4] , \CH391[0] , \MA[3] , 
        \next_MA[1] , \MAP[6] , \next_MA232[5] , \mprom_out[12] , \IR7_IR2[4] , 
        \mprom_out[21] , C20, \mprom_out[4] , \next_MA232[1] , \mprom_out[16] , 
        \IR7_IR2[0] , \MAP[2] , \mprom_out[9] , \mprom_out[0] , \mprom_out[2] , 
        \MAP[0] , \IR7_IR2[2] , \next_MA232[3] , \mprom_out[14] , 
        \mprom_out[6] , \mprom_out[19] , \next_MA232[7] , \mprom_out[10] , 
        \MAP[4] , \mprom_out[7] , \next_MA232[6] , \mprom_out[18] , 
        \mprom_out[11] , \MAP[5] , C19, \mprom_out[3] , \MAP[1] , 
        \next_MA232[2] , \mprom_out[15] , \IR7_IR2[3] , \IR7_IR2[1] , 
        \next_MA232[0] , \mprom_out[17] , \MAP[3] , \mprom_out[8] , 
        \mprom_out[1] , \MAP[7] , \mprom_out[13] , \next_MA232[4] , 
        \IR7_IR2[5] , \mprom_out[20] , \mprom_out[5] , \CH391[1] , \MA[2] , 
        \next_MA[0] , \next_MA[4] , \MA[6] , \MA182[1] , \MA[4] , \next_MA[6] , 
        \next_MA[2] , \CH391[3] , n649, n650, n651, n652, n653, n654, n655, 
        n656, n657, n658, n659, n660, n661, n662;
    maprom i_maprom ( .addr({\IR7_IR2[5] , \IR7_IR2[4] , \IR7_IR2[3] , 
        \IR7_IR2[2] , \IR7_IR2[1] , \IR7_IR2[0] }), .dout({\MAP[7] , \MAP[6] , 
        \MAP[5] , \MAP[4] , \MAP[3] , \MAP[2] , \MAP[1] , \MAP[0] }) );
    mprom i_mprom ( .addr({\MA[7] , \MA[6] , \MA[5] , \MA[4] , \MA[3] , 
        \MA[2] , \MA182[1] , \MA182[0] }), .dout({\mprom_out[21] , 
        \mprom_out[20] , \mprom_out[19] , \mprom_out[18] , \mprom_out[17] , 
        \mprom_out[16] , \mprom_out[15] , \mprom_out[14] , \mprom_out[13] , 
        \mprom_out[12] , \mprom_out[11] , \mprom_out[10] , \mprom_out[9] , 
        \mprom_out[8] , \mprom_out[7] , \mprom_out[6] , \mprom_out[5] , 
        \mprom_out[4] , \mprom_out[3] , \mprom_out[2] , \mprom_out[1] , 
        \mprom_out[0] }) );
    AN3P U233 ( .A(n660), .B(C20), .C(reset), .Z(n659) );
    IVP U234 ( .A(clock), .Z(n662) );
    IVP U235 ( .A(clock), .Z(n649) );
    IV U236 ( .A(n650), .Z(\MA[7] ) );
    IV U237 ( .A(n651), .Z(\MA[6] ) );
    IV U238 ( .A(n652), .Z(\MA[5] ) );
    IV U239 ( .A(n653), .Z(\MA[4] ) );
    IV U240 ( .A(n654), .Z(\MA[3] ) );
    IV U241 ( .A(n655), .Z(\MA[2] ) );
    IV U242 ( .A(n656), .Z(\MA182[1] ) );
    IV U243 ( .A(n657), .Z(\MA182[0] ) );
    IV U244 ( .A(\mprom_out[11] ), .Z(\CH391[4] ) );
    IV U245 ( .A(\mprom_out[10] ), .Z(\CH391[3] ) );
    IV U246 ( .A(\mprom_out[9] ), .Z(\CH391[2] ) );
    IV U247 ( .A(\mprom_out[8] ), .Z(\CH391[1] ) );
    IV U248 ( .A(\mprom_out[7] ), .Z(\CH391[0] ) );
    IV U249 ( .A(C19), .Z(n661) );
    AO2 U250 ( .A(n658), .B(\next_MA[7] ), .C(n659), .D(\MAP[7] ), .Z(n650) );
    AO2 U251 ( .A(\next_MA[6] ), .B(n658), .C(\MAP[6] ), .D(n659), .Z(n651) );
    AO2 U252 ( .A(\next_MA[5] ), .B(n658), .C(\MAP[5] ), .D(n659), .Z(n652) );
    AO2 U253 ( .A(\next_MA[4] ), .B(n658), .C(\MAP[4] ), .D(n659), .Z(n653) );
    AO2 U254 ( .A(\next_MA[3] ), .B(n658), .C(\MAP[3] ), .D(n659), .Z(n654) );
    AO2 U255 ( .A(\next_MA[2] ), .B(n658), .C(\MAP[2] ), .D(n659), .Z(n655) );
    AO2 U256 ( .A(\next_MA[1] ), .B(n658), .C(\MAP[1] ), .D(n659), .Z(n656) );
    AO2 U257 ( .A(\next_MA[0] ), .B(n658), .C(\MAP[0] ), .D(n659), .Z(n657) );
    AN3 U258 ( .A(C20), .B(C21), .C(reset), .Z(n658) );
    IV U259 ( .A(C21), .Z(n660) );
    FD2 \IR_reg[1]  ( .D(TDB[1]), .CP(n661), .CD(reset), .Q(IR[1]) );
    FD2 \IR_reg[0]  ( .D(TDB[0]), .CP(n661), .CD(reset), .Q(IR[0]) );
    FD2 \IR7_IR2_reg[5]  ( .D(TDB[7]), .CP(n661), .CD(reset), .Q(\IR7_IR2[5] )
         );
    FD2 \IR7_IR2_reg[4]  ( .D(TDB[6]), .CP(n661), .CD(reset), .Q(\IR7_IR2[4] )
         );
    FD2 \IR7_IR2_reg[3]  ( .D(TDB[5]), .CP(n661), .CD(reset), .Q(\IR7_IR2[3] )
         );
    FD2 \IR7_IR2_reg[2]  ( .D(TDB[4]), .CP(n661), .CD(reset), .Q(\IR7_IR2[2] )
         );
    FD2 \IR7_IR2_reg[1]  ( .D(TDB[3]), .CP(n661), .CD(reset), .Q(\IR7_IR2[1] )
         );
    FD2 \IR7_IR2_reg[0]  ( .D(TDB[2]), .CP(n661), .CD(reset), .Q(\IR7_IR2[0] )
         );
    FD2 \next_MA_reg[7]  ( .D(\next_MA232[7] ), .CP(n649), .CD(reset), .Q(
        \next_MA[7] ) );
    FD2 \next_MA_reg[6]  ( .D(\next_MA232[6] ), .CP(n649), .CD(reset), .Q(
        \next_MA[6] ) );
    FD2 \next_MA_reg[5]  ( .D(\next_MA232[5] ), .CP(n649), .CD(reset), .Q(
        \next_MA[5] ) );
    FD2 \next_MA_reg[4]  ( .D(\next_MA232[4] ), .CP(n649), .CD(reset), .Q(
        \next_MA[4] ) );
    FD2 \next_MA_reg[3]  ( .D(\next_MA232[3] ), .CP(n649), .CD(reset), .Q(
        \next_MA[3] ) );
    FD2 \next_MA_reg[2]  ( .D(\next_MA232[2] ), .CP(n649), .CD(reset), .Q(
        \next_MA[2] ) );
    FD2 \next_MA_reg[1]  ( .D(\next_MA232[1] ), .CP(n649), .CD(reset), .Q(
        \next_MA[1] ) );
    FD2 \next_MA_reg[0]  ( .D(\next_MA232[0] ), .CP(n649), .CD(reset), .Q(
        \next_MA[0] ) );
    FD2 \mux_sel_reg[2]  ( .D(\mprom_out[4] ), .CP(n649), .CD(reset), .Q(
        mux_sel[2]) );
    FD2 \mux_sel_reg[1]  ( .D(\mprom_out[3] ), .CP(n649), .CD(reset), .Q(
        mux_sel[1]) );
    FD2 \mux_sel_reg[0]  ( .D(\mprom_out[2] ), .CP(n649), .CD(reset), .Q(
        mux_sel[0]) );
    FD2 \CH_reg[4]  ( .D(\CH391[4] ), .CP(n649), .CD(reset), .Q(CH[4]) );
    FD2 \CH_reg[3]  ( .D(\CH391[3] ), .CP(n649), .CD(reset), .Q(CH[3]) );
    FD2 \CH_reg[2]  ( .D(\CH391[2] ), .CP(n649), .CD(reset), .Q(CH[2]) );
    FD2 \CH_reg[1]  ( .D(\CH391[1] ), .CP(n649), .CD(reset), .Q(CH[1]) );
    FD2 \CH_reg[0]  ( .D(\CH391[0] ), .CP(n662), .CD(reset), .Q(CH[0]) );
    FD2 \alu_mode_reg[2]  ( .D(\mprom_out[14] ), .CP(n662), .CD(reset), .Q(
        alu_mode[2]) );
    FD2 \alu_mode_reg[1]  ( .D(\mprom_out[13] ), .CP(n662), .CD(reset), .Q(
        alu_mode[1]) );
    FD2 \alu_mode_reg[0]  ( .D(\mprom_out[12] ), .CP(n662), .CD(reset), .Q(
        alu_mode[0]) );
    FD2 \bus_mode_reg[2]  ( .D(\mprom_out[17] ), .CP(n662), .CD(reset), .Q(
        bus_mode[2]) );
    FD2 \bus_mode_reg[1]  ( .D(\mprom_out[16] ), .CP(n662), .CD(reset), .Q(
        bus_mode[1]) );
    FD2 \bus_mode_reg[0]  ( .D(\mprom_out[15] ), .CP(n662), .CD(reset), .Q(
        bus_mode[0]) );
    FD2 C21_reg ( .D(\mprom_out[21] ), .CP(n662), .CD(reset), .Q(C21) );
    FD2 C5_reg ( .D(\mprom_out[5] ), .CP(n662), .CD(reset), .Q(C5) );
    FD2 C1_reg ( .D(\mprom_out[1] ), .CP(n662), .CD(reset), .Q(C1) );
    FD2 carry_mode_reg ( .D(\mprom_out[18] ), .CP(n662), .CD(reset), .Q(
        carry_mode) );
    FD2 C20_reg ( .D(\mprom_out[20] ), .CP(n662), .CD(reset), .Q(C20) );
    FD2 C0_reg ( .D(\mprom_out[0] ), .CP(n662), .CD(reset), .Q(C0) );
    FD2 C6_reg ( .D(\mprom_out[6] ), .CP(n662), .CD(reset), .Q(C6) );
    FD2 C19_reg ( .D(\mprom_out[19] ), .CP(n662), .CD(reset), .Q(C19) );
    CCU_DW01_inc_8_0 add_84 ( .A({\MA[7] , \MA[6] , \MA[5] , \MA[4] , \MA[3] , 
        \MA[2] , \MA182[1] , \MA182[0] }), .SUM({\next_MA232[7] , 
        \next_MA232[6] , \next_MA232[5] , \next_MA232[4] , \next_MA232[3] , 
        \next_MA232[2] , \next_MA232[1] , \next_MA232[0] }) );
endmodule


module CPU ( clock, reset, VMA, R_W, data, addr );
inout  [7:0] data;
output [7:0] addr;
input  clock, reset;
output VMA, R_W;
    wire S1, \IR[0] , \CH[2] , \alu_mode[1] , \mux_sel[1] , \ALU[6] , \PC[2] , 
        \TDB[2] , \IXR[6] , \ALU[2] , \IXR[2] , \bus_mode[1] , \ALU[0] , 
        \IXR[0] , \PC[6] , \PC[4] , \TDB[6] , \TDB[4] , \CH[4] , \IR[1] , 
        \PC[1] , \PC[0] , \ALU[4] , \IXR[4] , C6, \TDB[0] , \CH[0] , 
        carry_mode, \ALU[5] , \IXR[5] , error, \TDB[1] , \CH[1] , \ALU[1] , 
        \mux_sel[2] , \PC[5] , \alu_mode[2] , \TDB[5] , \bus_mode[2] , 
        \IXR[1] , \ALU[3] , \bus_mode[0] , \IXR[3] , \PC[7] , \TDB[7] , 
        \alu_mode[0] , \ALU[7] , \IXR[7] , \mux_sel[0] , \PC[3] , \TDB[3] , 
        \CH[3] , C5;
    ALUB i_ALUB ( .IR({\IR[1] , \IR[0] }), .IDB(addr), .PC({\PC[7] , \PC[6] , 
        \PC[5] , \PC[4] , \PC[3] , \PC[2] , \PC[1] , \PC[0] }), .CH({\CH[4] , 
        \CH[3] , \CH[2] , \CH[1] , \CH[0] }), .alu_mode({\alu_mode[2] , 
        \alu_mode[1] , \alu_mode[0] }), .bus_mode({\bus_mode[2] , 
        \bus_mode[1] , \bus_mode[0] }), .carry_mode(carry_mode), .clock(clock), 
        .reset(reset), .S1(S1), .ALU({\ALU[7] , \ALU[6] , \ALU[5] , \ALU[4] , 
        \ALU[3] , \ALU[2] , \ALU[1] , \ALU[0] }), .IXR({\IXR[7] , \IXR[6] , 
        \IXR[5] , \IXR[4] , \IXR[3] , \IXR[2] , \IXR[1] , \IXR[0] }), 
        .error_out(error) );
    PCU i_PCU ( .mux_sel({\mux_sel[2] , \mux_sel[1] , \mux_sel[0] }), .C6(C6), 
        .C5(C5), .C1(R_W), .ALU({\ALU[7] , \ALU[6] , \ALU[5] , \ALU[4] , 
        \ALU[3] , \ALU[2] , \ALU[1] , \ALU[0] }), .S1(S1), .IXR({\IXR[7] , 
        \IXR[6] , \IXR[5] , \IXR[4] , \IXR[3] , \IXR[2] , \IXR[1] , \IXR[0] }), 
        .reset(reset), .data(data), .PC({\PC[7] , \PC[6] , \PC[5] , \PC[4] , 
        \PC[3] , \PC[2] , \PC[1] , \PC[0] }), .IDB(addr), .TDB({\TDB[7] , 
        \TDB[6] , \TDB[5] , \TDB[4] , \TDB[3] , \TDB[2] , \TDB[1] , \TDB[0] }), 
        .error_in(error) );
    CCU i_CCU ( .TDB({\TDB[7] , \TDB[6] , \TDB[5] , \TDB[4] , \TDB[3] , 
        \TDB[2] , \TDB[1] , \TDB[0] }), .clock(clock), .reset(reset), .CH({
        \CH[4] , \CH[3] , \CH[2] , \CH[1] , \CH[0] }), .alu_mode({
        \alu_mode[2] , \alu_mode[1] , \alu_mode[0] }), .bus_mode({
        \bus_mode[2] , \bus_mode[1] , \bus_mode[0] }), .carry_mode(carry_mode), 
        .mux_sel({\mux_sel[2] , \mux_sel[1] , \mux_sel[0] }), .C6(C6), .C5(C5), 
        .C1(R_W), .C0(VMA), .IR({\IR[1] , \IR[0] }) );
endmodule