cpu.vg

debussy中文使用手册

    IV U8 ( .A(A[8]), .Z(n3) );
    AN2 U9 ( .A(\carry[6] ), .B(A[6]), .Z(\carry[7] ) );
    MUX21H U10 ( .S(\carry[6] ), .A(A[6]), .B(n4), .Z(SUM[6]) );
    IV U11 ( .A(A[6]), .Z(n4) );
    AN2 U12 ( .A(\carry[5] ), .B(A[5]), .Z(\carry[6] ) );
    MUX21H U13 ( .S(\carry[5] ), .A(A[5]), .B(n27), .Z(SUM[5]) );
    IV U14 ( .A(A[5]), .Z(n27) );
    AN2 U15 ( .A(\carry[4] ), .B(A[4]), .Z(\carry[5] ) );
    MUX21H U16 ( .S(\carry[4] ), .A(A[4]), .B(n28), .Z(SUM[4]) );
    IV U17 ( .A(A[4]), .Z(n28) );
    AN2 U18 ( .A(\carry[3] ), .B(A[3]), .Z(\carry[4] ) );
    MUX21H U19 ( .S(\carry[3] ), .A(A[3]), .B(n29), .Z(SUM[3]) );
    IV U20 ( .A(A[3]), .Z(n29) );
    AN2 U21 ( .A(\carry[2] ), .B(A[2]), .Z(\carry[3] ) );
    MUX21H U22 ( .S(\carry[2] ), .A(A[2]), .B(n30), .Z(SUM[2]) );
    IV U23 ( .A(A[2]), .Z(n30) );
    AN2 U24 ( .A(A[0]), .B(B[0]), .Z(\carry[1] ) );
    MUX21H U25 ( .S(A[0]), .A(B[0]), .B(n31), .Z(SUM[0]) );
    IV U26 ( .A(B[0]), .Z(n31) );
endmodule


module alu_DW01_add_9_2 ( A, B, CI, SUM, CO );
input  [8:0] A;
input  [8:0] B;
output [8:0] SUM;
input  CI;
output CO;
    wire \carry[4] , \carry[6] , \carry[2] , \carry[8] , \carry[7] , 
        \carry[3] , \carry[5] , \carry[1] , n32, n33, n34, n35, n36, n37, n38, 
        n39, n40;
    MUX21H U1 ( .S(\carry[8] ), .A(A[8]), .B(n32), .Z(SUM[8]) );
    IV U2 ( .A(A[8]), .Z(n32) );
    AN2 U3 ( .A(\carry[7] ), .B(A[7]), .Z(\carry[8] ) );
    MUX21H U4 ( .S(\carry[7] ), .A(A[7]), .B(n33), .Z(SUM[7]) );
    IV U5 ( .A(A[7]), .Z(n33) );
    AN2 U6 ( .A(\carry[6] ), .B(A[6]), .Z(\carry[7] ) );
    MUX21H U7 ( .S(\carry[6] ), .A(A[6]), .B(n34), .Z(SUM[6]) );
    IV U8 ( .A(A[6]), .Z(n34) );
    AN2 U9 ( .A(\carry[5] ), .B(A[5]), .Z(\carry[6] ) );
    MUX21H U10 ( .S(\carry[5] ), .A(A[5]), .B(n35), .Z(SUM[5]) );
    IV U11 ( .A(A[5]), .Z(n35) );
    AN2 U12 ( .A(\carry[4] ), .B(A[4]), .Z(\carry[5] ) );
    MUX21H U13 ( .S(\carry[4] ), .A(A[4]), .B(n36), .Z(SUM[4]) );
    IV U14 ( .A(A[4]), .Z(n36) );
    AN2 U15 ( .A(\carry[3] ), .B(A[3]), .Z(\carry[4] ) );
    MUX21H U16 ( .S(\carry[3] ), .A(A[3]), .B(n37), .Z(SUM[3]) );
    IV U17 ( .A(A[3]), .Z(n37) );
    AN2 U18 ( .A(\carry[2] ), .B(A[2]), .Z(\carry[3] ) );
    MUX21H U19 ( .S(\carry[2] ), .A(A[2]), .B(n38), .Z(SUM[2]) );
    IV U20 ( .A(A[2]), .Z(n38) );
    AN2 U21 ( .A(\carry[1] ), .B(A[1]), .Z(\carry[2] ) );
    MUX21H U22 ( .S(\carry[1] ), .A(A[1]), .B(n39), .Z(SUM[1]) );
    IV U23 ( .A(A[1]), .Z(n39) );
    AN2 U24 ( .A(A[0]), .B(B[0]), .Z(\carry[1] ) );
    MUX21H U25 ( .S(A[0]), .A(B[0]), .B(n40), .Z(SUM[0]) );
    IV U26 ( .A(B[0]), .Z(n40) );
endmodule


module alu_DW01_add_9_1 ( A, B, CI, SUM, CO );
input  [8:0] A;
input  [8:0] B;
output [8:0] SUM;
input  CI;
output CO;
    wire \carry[4] , \carry[6] , \carry[2] , \carry[7] , \carry[3] , 
        \carry[5] , \carry[1] ;
    FA1 U1_0 ( .A(A[0]), .B(B[0]), .CI(1'b0), .S(SUM[0]), .CO(\carry[1] ) );
    FA1 U1_1 ( .A(A[1]), .B(B[1]), .CI(\carry[1] ), .S(SUM[1]), .CO(\carry[2] 
        ) );
    FA1 U1_6 ( .A(A[6]), .B(B[6]), .CI(\carry[6] ), .S(SUM[6]), .CO(\carry[7] 
        ) );
    FA1 U1_7 ( .A(A[7]), .B(B[7]), .CI(\carry[7] ), .S(SUM[7]), .CO(SUM[8]) );
    FA1 U1_2 ( .A(A[2]), .B(B[2]), .CI(\carry[2] ), .S(SUM[2]), .CO(\carry[3] 
        ) );
    FA1 U1_3 ( .A(A[3]), .B(B[3]), .CI(\carry[3] ), .S(SUM[3]), .CO(\carry[4] 
        ) );
    FA1 U1_4 ( .A(A[4]), .B(B[4]), .CI(\carry[4] ), .S(SUM[4]), .CO(\carry[5] 
        ) );
    FA1 U1_5 ( .A(A[5]), .B(B[5]), .CI(\carry[5] ), .S(SUM[5]), .CO(\carry[6] 
        ) );
endmodule


module alu_DW01_sub_9_0 ( A, B, CI, DIFF, CO );
input  [8:0] A;
input  [8:0] B;
output [8:0] DIFF;
input  CI;
output CO;
    wire \carry[4] , \B_not[3] , \carry[6] , \carry[2] , \B_not[7] , 
        \B_not[5] , \B_not[1] , \carry[8] , \carry[7] , \B_not[0] , \carry[3] , 
        \B_not[4] , \carry[5] , \carry[1] , \B_not[6] , \B_not[2] ;
    IV U3 ( .A(\carry[8] ), .Z(DIFF[8]) );
    IV U4 ( .A(B[4]), .Z(\B_not[4] ) );
    IV U5 ( .A(B[3]), .Z(\B_not[3] ) );
    IV U6 ( .A(B[5]), .Z(\B_not[5] ) );
    IV U7 ( .A(B[2]), .Z(\B_not[2] ) );
    IV U8 ( .A(B[7]), .Z(\B_not[7] ) );
    IV U9 ( .A(B[6]), .Z(\B_not[6] ) );
    IV U10 ( .A(B[0]), .Z(\B_not[0] ) );
    IV U11 ( .A(B[1]), .Z(\B_not[1] ) );
    FA1 U2_4 ( .A(A[4]), .B(\B_not[4] ), .CI(\carry[4] ), .S(DIFF[4]), .CO(
        \carry[5] ) );
    FA1 U2_2 ( .A(A[2]), .B(\B_not[2] ), .CI(\carry[2] ), .S(DIFF[2]), .CO(
        \carry[3] ) );
    FA1 U2_3 ( .A(A[3]), .B(\B_not[3] ), .CI(\carry[3] ), .S(DIFF[3]), .CO(
        \carry[4] ) );
    FA1 U2_0 ( .A(A[0]), .B(\B_not[0] ), .CI(1'b1), .S(DIFF[0]), .CO(
        \carry[1] ) );
    FA1 U2_5 ( .A(A[5]), .B(\B_not[5] ), .CI(\carry[5] ), .S(DIFF[5]), .CO(
        \carry[6] ) );
    FA1 U2_7 ( .A(A[7]), .B(\B_not[7] ), .CI(\carry[7] ), .S(DIFF[7]), .CO(
        \carry[8] ) );
    FA1 U2_1 ( .A(A[1]), .B(\B_not[1] ), .CI(\carry[1] ), .S(DIFF[1]), .CO(
        \carry[2] ) );
    FA1 U2_6 ( .A(A[6]), .B(\B_not[6] ), .CI(\carry[6] ), .S(DIFF[6]), .CO(
        \carry[7] ) );
endmodule


module alu_DW01_add_9_0 ( A, B, CI, SUM, CO );
input  [8:0] A;
input  [8:0] B;
output [8:0] SUM;
input  CI;
output CO;
    wire \carry[4] , \carry[6] , \carry[2] , \carry[8] , \carry[7] , 
        \carry[3] , \carry[5] , \carry[1] , n43, n44, n45, n46, n47, n48, n49, 
        n50, n51;
    MUX21H U1 ( .S(\carry[8] ), .A(A[8]), .B(n43), .Z(SUM[8]) );
    IV U2 ( .A(A[8]), .Z(n43) );
    AN2 U3 ( .A(\carry[7] ), .B(A[7]), .Z(\carry[8] ) );
    MUX21H U4 ( .S(\carry[7] ), .A(A[7]), .B(n44), .Z(SUM[7]) );
    IV U5 ( .A(A[7]), .Z(n44) );
    AN2 U6 ( .A(\carry[6] ), .B(A[6]), .Z(\carry[7] ) );
    MUX21H U7 ( .S(\carry[6] ), .A(A[6]), .B(n45), .Z(SUM[6]) );
    IV U8 ( .A(A[6]), .Z(n45) );
    AN2 U9 ( .A(\carry[5] ), .B(A[5]), .Z(\carry[6] ) );
    MUX21H U10 ( .S(\carry[5] ), .A(A[5]), .B(n46), .Z(SUM[5]) );
    IV U11 ( .A(A[5]), .Z(n46) );
    AN2 U12 ( .A(\carry[4] ), .B(A[4]), .Z(\carry[5] ) );
    MUX21H U13 ( .S(\carry[4] ), .A(A[4]), .B(n47), .Z(SUM[4]) );
    IV U14 ( .A(A[4]), .Z(n47) );
    AN2 U15 ( .A(\carry[3] ), .B(A[3]), .Z(\carry[4] ) );
    MUX21H U16 ( .S(\carry[3] ), .A(A[3]), .B(n48), .Z(SUM[3]) );
    IV U17 ( .A(A[3]), .Z(n48) );
    AN2 U18 ( .A(\carry[2] ), .B(A[2]), .Z(\carry[3] ) );
    MUX21H U19 ( .S(\carry[2] ), .A(A[2]), .B(n49), .Z(SUM[2]) );
    IV U20 ( .A(A[2]), .Z(n49) );
    AN2 U21 ( .A(\carry[1] ), .B(A[1]), .Z(\carry[2] ) );
    MUX21H U22 ( .S(\carry[1] ), .A(A[1]), .B(n50), .Z(SUM[1]) );
    IV U23 ( .A(A[1]), .Z(n50) );
    AN2 U24 ( .A(A[0]), .B(B[0]), .Z(\carry[1] ) );
    MUX21H U25 ( .S(A[0]), .A(B[0]), .B(n51), .Z(SUM[0]) );
    IV U26 ( .A(B[0]), .Z(n51) );
endmodule


module alu_DW01_dec_9_0 ( A, SUM );
input  [8:0] A;
output [8:0] SUM;
    wire n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, 
        n66, n67, n68, n69, n70, n71, n72;
    ND2 U3 ( .A(n52), .B(n53), .Z(SUM[2]) );
    IV U4 ( .A(A[0]), .Z(SUM[0]) );
    ND2 U5 ( .A(n54), .B(n55), .Z(SUM[6]) );
    ND2 U6 ( .A(n56), .B(n57), .Z(SUM[3]) );
    ND2 U7 ( .A(n58), .B(n59), .Z(SUM[4]) );
    ND2 U8 ( .A(n60), .B(n61), .Z(SUM[5]) );
    ND2 U9 ( .A(n62), .B(n63), .Z(SUM[1]) );
    NR2 U10 ( .A(A[7]), .B(n54), .Z(n64) );
    NR2 U11 ( .A(A[0]), .B(A[1]), .Z(n65) );
    NR2 U12 ( .A(n62), .B(A[2]), .Z(n66) );
    NR2 U13 ( .A(n52), .B(A[3]), .Z(n67) );
    NR2 U14 ( .A(n56), .B(A[4]), .Z(n68) );
    NR2 U15 ( .A(n58), .B(A[5]), .Z(n69) );
    NR2 U16 ( .A(n60), .B(A[6]), .Z(n70) );
    MUX21H U17 ( .S(n64), .A(A[8]), .B(n71), .Z(SUM[8]) );
    MUX21H U18 ( .S(n70), .A(A[7]), .B(n72), .Z(SUM[7]) );
    ND2 U19 ( .A(A[6]), .B(n60), .Z(n55) );
    ND2 U20 ( .A(A[5]), .B(n58), .Z(n61) );
    ND2 U21 ( .A(A[4]), .B(n56), .Z(n59) );
    ND2 U22 ( .A(A[3]), .B(n52), .Z(n57) );
    ND2 U23 ( .A(A[2]), .B(n62), .Z(n53) );
    ND2 U24 ( .A(A[1]), .B(A[0]), .Z(n63) );
    IV U25 ( .A(A[8]), .Z(n71) );
    IV U26 ( .A(A[7]), .Z(n72) );
    IV U27 ( .A(n65), .Z(n62) );
    IV U28 ( .A(n67), .Z(n56) );
    IV U29 ( .A(n66), .Z(n52) );
    IV U30 ( .A(n69), .Z(n60) );
    IV U31 ( .A(n68), .Z(n58) );
    IV U32 ( .A(n70), .Z(n54) );
endmodule


module alu ( a, b, cin, select, out, carry, zero );
input  [7:0] a;
input  [2:0] select;
input  [7:0] b;
output [7:0] out;
input  cin;
output carry, zero;
    wire \b320[9] , \n130[27] , \b320[4] , \b320[6] , \n130[25] , \b320[2] , 
        \n130[28] , \n130[31] , \b337[2] , \n142[25] , \n133[24] , \b303[7] , 
        \n139[32] , \n136[25] , \n136[28] , \n136[31] , \n139[26] , \b337[6] , 
        \n133[29] , \n133[30] , \b303[3] , \n142[28] , \n142[31] , \n133[32] , 
        \b303[1] , \n139[24] , \b337[4] , \b303[8] , \n139[29] , \n139[30] , 
        \b337[9] , \n136[27] , \b303[5] , \n133[26] , \n142[27] , \b337[8] , 
        \n139[28] , \n139[31] , \n136[26] , \b303[4] , \n142[26] , \n133[27] , 
        \b337[1] , \n142[32] , \n136[32] , \b337[5] , \n139[25] , \b303[9] , 
        \n136[29] , \n136[30] , \n139[27] , \b337[7] , \n133[28] , \n133[31] , 
        \n142[30] , \n142[29] , \b303[2] , \b337[3] , \n142[24] , \n133[25] , 
        \b303[6] , \n136[24] , \b320[3] , \n130[29] , \n130[30] , \b320[7] , 
        \n130[24] , \n130[26] , \b320[5] , \n130[32] , \b320[8] , \b320[1] , 
        n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, 
        n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498, 
        n499, n500, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, 
        n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, 
        n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, 
        n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, 
        n593, n594, n595, n596, n597, n598, n599, n600, n601, n602;
    OR3P U98 ( .A(select[1]), .B(select[0]), .C(n562), .Z(n564) );
    AN3P U99 ( .A(n562), .B(n565), .C(select[1]), .Z(n558) );
    NR2 U100 ( .A(n475), .B(n476), .Z(zero) );
    OR4 U101 ( .A(n477), .B(n478), .C(n479), .D(n480), .Z(out[7]) );
    OR4 U102 ( .A(n481), .B(n482), .C(n483), .D(n484), .Z(out[6]) );
    OR4 U103 ( .A(n485), .B(n486), .C(n487), .D(n488), .Z(out[5]) );
    OR4 U104 ( .A(n489), .B(n490), .C(n491), .D(n492), .Z(out[4]) );
    OR4 U105 ( .A(n493), .B(n494), .C(n495), .D(n496), .Z(out[3]) );
    OR4 U106 ( .A(n497), .B(n498), .C(n499), .D(n500), .Z(out[2]) );
    OR4 U107 ( .A(n547), .B(n548), .C(n549), .D(n550), .Z(out[1]) );
    OR4 U108 ( .A(n551), .B(n552), .C(n553), .D(n554), .Z(out[0]) );
    AN2 U109 ( .A(\b320[8] ), .B(n555), .Z(n479) );
    AN2 U110 ( .A(\b337[8] ), .B(n556), .Z(n477) );
    AN2 U111 ( .A(\b320[7] ), .B(n555), .Z(n483) );
    AN2 U112 ( .A(\b337[7] ), .B(n556), .Z(n481) );