📄 cpu.vg
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// ************************************************************************// * NOVAS SOFTWARE CONFIDENTIAL PROPRIETARY NOTE *// * *// * This software contains information confidential and proprietary *// * to Novas Software Inc. It shall not be reproduced in whole *// * or in part or transferred to other documents, or disclosed *// * to third parties, or used for any purpose other than that *// * for which it was obtained, without the prior written consent *// * of Novas Software Inc. *// * (c) 1996, 1997, 1998 Novas Software Inc. *// * All rights reserved *// * *// ************************************************************************module PCU ( mux_sel, C6, C5, C1, ALU, S1, IXR, reset, data, PC, IDB, TDB, error_in );input [2:0] mux_sel;input [7:0] ALU;input [7:0] IXR;output [7:0] PC;output [7:0] TDB;inout [7:0] data;output [7:0] IDB;input C6, C5, C1, S1, reset, error_in; wire \TDB374[1] , \IDR126[2] , \TR[1] , \TDB374[5] , \IDR[7] , \TR[5] , \IDR126[6] , \TR[7] , \IDR126[4] , \IDR[5] , \TDB374[7] , \IDR[1] , \IDR126[0] , \TR[3] , \TDB374[3] , \IDR[0] , \IDR126[1] , \TR[2] , \TDB374[2] , \TR[6] , \IDR126[5] , \IDR[4] , \TDB374[6] , \TDB374[4] , \IDR[6] , \TR[4] , \IDR126[7] , \TDB374[0] , \IDR126[3] , \TR[0] , \IDR[2] , \IDR_Q130[3] , n501, n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546; AN3P U168 ( .A(n522), .B(mux_sel[1]), .C(mux_sel[0]), .Z(n525) ); AN3P U169 ( .A(n522), .B(n519), .C(mux_sel[0]), .Z(n523) ); AN3P U170 ( .A(n522), .B(n520), .C(mux_sel[1]), .Z(n521) ); ND2 U171 ( .A(n501), .B(n502), .Z(IDB[7]) ); ND2 U172 ( .A(n503), .B(n504), .Z(IDB[6]) ); ND2 U173 ( .A(n505), .B(n506), .Z(IDB[5]) ); ND2 U174 ( .A(n507), .B(n508), .Z(IDB[4]) ); ND2 U175 ( .A(n509), .B(n510), .Z(IDB[3]) ); ND2 U176 ( .A(n511), .B(n512), .Z(IDB[2]) ); ND2 U177 ( .A(n513), .B(n514), .Z(IDB[1]) ); ND2 U178 ( .A(n515), .B(n516), .Z(IDB[0]) ); AN2 U179 ( .A(data[7]), .B(n517), .Z(\TDB374[7] ) ); AN2 U180 ( .A(data[6]), .B(n517), .Z(\TDB374[6] ) ); AN2 U181 ( .A(data[5]), .B(n517), .Z(\TDB374[5] ) ); AN2 U182 ( .A(data[4]), .B(n517), .Z(\TDB374[4] ) ); AN2 U183 ( .A(data[3]), .B(n517), .Z(\TDB374[3] ) ); AN2 U184 ( .A(data[2]), .B(n517), .Z(\TDB374[2] ) ); AN2 U185 ( .A(data[1]), .B(n517), .Z(\TDB374[1] ) ); AN2 U186 ( .A(data[0]), .B(n517), .Z(\TDB374[0] ) ); AN2 U187 ( .A(n517), .B(n542), .Z(n546) ); IV U188 ( .A(C6), .Z(n545) ); IV U189 ( .A(S1), .Z(n544) ); IV U190 ( .A(C5), .Z(n543) ); IV U191 ( .A(C1), .Z(n542) ); AN3 U192 ( .A(n519), .B(n520), .C(mux_sel[2]), .Z(n518) ); AN3 U193 ( .A(n522), .B(n519), .C(n520), .Z(n524) ); MUX21H U194 ( .S(C1), .A(IDB[7]), .B(TDB[7]), .Z(\IDR126[7] ) ); MUX21H U195 ( .S(C1), .A(IDB[6]), .B(TDB[6]), .Z(\IDR126[6] ) ); MUX21H U196 ( .S(C1), .A(IDB[5]), .B(TDB[5]), .Z(\IDR126[5] ) ); MUX21H U197 ( .S(C1), .A(IDB[4]), .B(TDB[4]), .Z(\IDR126[4] ) ); MUX21H U198 ( .S(C1), .A(IDB[3]), .B(TDB[3]), .Z(\IDR126[3] ) ); MUX21H U199 ( .S(C1), .A(IDB[2]), .B(TDB[2]), .Z(\IDR126[2] ) ); MUX21H U200 ( .S(C1), .A(IDB[1]), .B(TDB[1]), .Z(\IDR126[1] ) ); MUX21H U201 ( .S(C1), .A(IDB[0]), .B(TDB[0]), .Z(\IDR126[0] ) ); AO2 U202 ( .A(n518), .B(IXR[7]), .C(n521), .D(\TR[7] ), .Z(n526) ); AN2 U203 ( .A(n526), .B(n527), .Z(n502) ); AO2 U204 ( .A(n524), .B(\IDR[7] ), .C(n525), .D(ALU[7]), .Z(n501) ); AO2 U205 ( .A(IXR[6]), .B(n518), .C(\TR[6] ), .D(n521), .Z(n528) ); AN2 U206 ( .A(n528), .B(n529), .Z(n504) ); AO2 U207 ( .A(\IDR[6] ), .B(n524), .C(ALU[6]), .D(n525), .Z(n503) ); AO2 U208 ( .A(IXR[5]), .B(n518), .C(\TR[5] ), .D(n521), .Z(n530) ); AN2 U209 ( .A(n530), .B(n531), .Z(n506) ); AO2 U210 ( .A(\IDR[5] ), .B(n524), .C(ALU[5]), .D(n525), .Z(n505) ); AO2 U211 ( .A(IXR[4]), .B(n518), .C(\TR[4] ), .D(n521), .Z(n532) ); AN2 U212 ( .A(n532), .B(n533), .Z(n508) ); AO2 U213 ( .A(\IDR[4] ), .B(n524), .C(ALU[4]), .D(n525), .Z(n507) ); AO2 U214 ( .A(IXR[3]), .B(n518), .C(\TR[3] ), .D(n521), .Z(n534) ); AN2 U215 ( .A(n534), .B(n535), .Z(n510) ); AO2 U216 ( .A(\IDR_Q130[3] ), .B(n524), .C(ALU[3]), .D(n525), .Z(n509) ); AO2 U217 ( .A(IXR[2]), .B(n518), .C(\TR[2] ), .D(n521), .Z(n536) ); AN2 U218 ( .A(n536), .B(n537), .Z(n512) ); AO2 U219 ( .A(\IDR[2] ), .B(n524), .C(ALU[2]), .D(n525), .Z(n511) ); AO2 U220 ( .A(IXR[1]), .B(n518), .C(\TR[1] ), .D(n521), .Z(n538) ); AN2 U221 ( .A(n538), .B(n539), .Z(n514) ); AO2 U222 ( .A(\IDR[1] ), .B(n524), .C(ALU[1]), .D(n525), .Z(n513) ); AO2 U223 ( .A(IXR[0]), .B(n518), .C(\TR[0] ), .D(n521), .Z(n540) ); AN2 U224 ( .A(n540), .B(n541), .Z(n516) ); AO2 U225 ( .A(\IDR[0] ), .B(n524), .C(ALU[0]), .D(n525), .Z(n515) ); ND2 U226 ( .A(reset), .B(error_in), .Z(n517) ); ND2 U227 ( .A(n523), .B(PC[7]), .Z(n527) ); ND2 U228 ( .A(PC[6]), .B(n523), .Z(n529) ); ND2 U229 ( .A(PC[5]), .B(n523), .Z(n531) ); ND2 U230 ( .A(PC[4]), .B(n523), .Z(n533) ); ND2 U231 ( .A(PC[3]), .B(n523), .Z(n535) ); ND2 U232 ( .A(PC[2]), .B(n523), .Z(n537) ); ND2 U233 ( .A(PC[1]), .B(n523), .Z(n539) ); ND2 U234 ( .A(PC[0]), .B(n523), .Z(n541) ); IV U235 ( .A(mux_sel[2]), .Z(n522) ); IV U236 ( .A(mux_sel[1]), .Z(n519) ); IV U237 ( .A(mux_sel[0]), .Z(n520) ); BTS4 U238 ( .A(\IDR[7] ), .E(n542), .Z(data[7]) ); BTS4 U239 ( .A(\IDR_Q130[3] ), .E(n542), .Z(data[3]) ); BTS4 U240 ( .A(\IDR[1] ), .E(n542), .Z(data[1]) ); BTS4 U241 ( .A(\IDR[5] ), .E(n542), .Z(data[5]) ); BTS4 U242 ( .A(\IDR[4] ), .E(n542), .Z(data[4]) ); BTS4 U243 ( .A(\IDR[0] ), .E(n542), .Z(data[0]) ); BTS4 U244 ( .A(\IDR[2] ), .E(n542), .Z(data[2]) ); BTS4 U245 ( .A(\IDR[6] ), .E(n542), .Z(data[6]) ); FD2 \IDR_reg[7] ( .D(\IDR126[7] ), .CP(n543), .CD(reset), .Q(\IDR[7] ) ); FD2 \IDR_reg[6] ( .D(\IDR126[6] ), .CP(n543), .CD(reset), .Q(\IDR[6] ) ); FD2 \IDR_reg[5] ( .D(\IDR126[5] ), .CP(n543), .CD(reset), .Q(\IDR[5] ) ); FD2 \IDR_reg[4] ( .D(\IDR126[4] ), .CP(n543), .CD(reset), .Q(\IDR[4] ) ); FD2 \IDR_reg[3] ( .D(\IDR126[3] ), .CP(n543), .CD(reset), .Q( \IDR_Q130[3] ) ); FD2 \IDR_reg[2] ( .D(\IDR126[2] ), .CP(n543), .CD(reset), .Q(\IDR[2] ) ); FD2 \IDR_reg[1] ( .D(\IDR126[1] ), .CP(n543), .CD(reset), .Q(\IDR[1] ) ); FD2 \IDR_reg[0] ( .D(\IDR126[0] ), .CP(n543), .CD(reset), .Q(\IDR[0] ) ); FD2 \PC_reg[7] ( .D(ALU[7]), .CP(n544), .CD(reset), .Q(PC[7]) ); FD2 \PC_reg[6] ( .D(ALU[6]), .CP(n544), .CD(reset), .Q(PC[6]) ); FD2 \PC_reg[5] ( .D(ALU[5]), .CP(n544), .CD(reset), .Q(PC[5]) ); FD2 \PC_reg[4] ( .D(ALU[4]), .CP(n544), .CD(reset), .Q(PC[4]) ); FD2 \PC_reg[3] ( .D(ALU[3]), .CP(n544), .CD(reset), .Q(PC[3]) ); FD2 \PC_reg[2] ( .D(ALU[2]), .CP(n544), .CD(reset), .Q(PC[2]) ); FD2 \PC_reg[1] ( .D(ALU[1]), .CP(n544), .CD(reset), .Q(PC[1]) ); FD2 \PC_reg[0] ( .D(ALU[0]), .CP(n544), .CD(reset), .Q(PC[0]) ); FD2 \TR_reg[7] ( .D(ALU[7]), .CP(n545), .CD(reset), .Q(\TR[7] ) ); FD2 \TR_reg[6] ( .D(ALU[6]), .CP(n545), .CD(reset), .Q(\TR[6] ) ); FD2 \TR_reg[5] ( .D(ALU[5]), .CP(n545), .CD(reset), .Q(\TR[5] ) ); FD2 \TR_reg[4] ( .D(ALU[4]), .CP(n545), .CD(reset), .Q(\TR[4] ) ); FD2 \TR_reg[3] ( .D(ALU[3]), .CP(n545), .CD(reset), .Q(\TR[3] ) ); FD2 \TR_reg[2] ( .D(ALU[2]), .CP(n545), .CD(reset), .Q(\TR[2] ) ); FD2 \TR_reg[1] ( .D(ALU[1]), .CP(n545), .CD(reset), .Q(\TR[1] ) ); FD2 \TR_reg[0] ( .D(ALU[0]), .CP(n545), .CD(reset), .Q(\TR[0] ) ); LD2 \TDB_reg[7] ( .D(\TDB374[7] ), .GN(n546), .Q(TDB[7]) ); LD2 \TDB_reg[6] ( .D(\TDB374[6] ), .GN(n546), .Q(TDB[6]) ); LD2 \TDB_reg[5] ( .D(\TDB374[5] ), .GN(n546), .Q(TDB[5]) ); LD2 \TDB_reg[4] ( .D(\TDB374[4] ), .GN(n546), .Q(TDB[4]) ); LD2 \TDB_reg[3] ( .D(\TDB374[3] ), .GN(n546), .Q(TDB[3]) ); LD2 \TDB_reg[2] ( .D(\TDB374[2] ), .GN(n546), .Q(TDB[2]) ); LD2 \TDB_reg[1] ( .D(\TDB374[1] ), .GN(n546), .Q(TDB[1]) ); LD2 \TDB_reg[0] ( .D(\TDB374[0] ), .GN(n546), .Q(TDB[0]) );endmodulemodule alu_DW01_sub_9_1 ( A, B, CI, DIFF, CO );input [8:0] A;input [8:0] B;output [8:0] DIFF;input CI;output CO; wire \carry[4] , \B_not[3] , \carry[6] , \carry[2] , \B_not[7] , \B_not[5] , \B_not[1] , \carry[8] , \carry[7] , \B_not[0] , \carry[3] , \B_not[4] , \carry[5] , \carry[1] , \B_not[6] , \B_not[2] ; IV U3 ( .A(\carry[8] ), .Z(DIFF[8]) ); IV U4 ( .A(B[4]), .Z(\B_not[4] ) ); IV U5 ( .A(B[3]), .Z(\B_not[3] ) ); IV U6 ( .A(B[5]), .Z(\B_not[5] ) ); IV U7 ( .A(B[2]), .Z(\B_not[2] ) ); IV U8 ( .A(B[7]), .Z(\B_not[7] ) ); IV U9 ( .A(B[6]), .Z(\B_not[6] ) ); IV U10 ( .A(B[0]), .Z(\B_not[0] ) ); IV U11 ( .A(B[1]), .Z(\B_not[1] ) ); FA1 U2_4 ( .A(A[4]), .B(\B_not[4] ), .CI(\carry[4] ), .S(DIFF[4]), .CO( \carry[5] ) ); FA1 U2_2 ( .A(A[2]), .B(\B_not[2] ), .CI(\carry[2] ), .S(DIFF[2]), .CO( \carry[3] ) ); FA1 U2_3 ( .A(A[3]), .B(\B_not[3] ), .CI(\carry[3] ), .S(DIFF[3]), .CO( \carry[4] ) ); FA1 U2_0 ( .A(A[0]), .B(\B_not[0] ), .CI(1'b1), .S(DIFF[0]), .CO( \carry[1] ) ); FA1 U2_5 ( .A(A[5]), .B(\B_not[5] ), .CI(\carry[5] ), .S(DIFF[5]), .CO( \carry[6] ) ); FA1 U2_7 ( .A(A[7]), .B(\B_not[7] ), .CI(\carry[7] ), .S(DIFF[7]), .CO( \carry[8] ) ); FA1 U2_1 ( .A(A[1]), .B(\B_not[1] ), .CI(\carry[1] ), .S(DIFF[1]), .CO( \carry[2] ) ); FA1 U2_6 ( .A(A[6]), .B(\B_not[6] ), .CI(\carry[6] ), .S(DIFF[6]), .CO( \carry[7] ) );endmodulemodule alu_DW01_dec_9_1 ( A, SUM );input [8:0] A;output [8:0] SUM; wire n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26; ND2 U3 ( .A(n6), .B(n7), .Z(SUM[2]) ); IV U4 ( .A(A[0]), .Z(SUM[0]) ); ND2 U5 ( .A(n8), .B(n9), .Z(SUM[6]) ); ND2 U6 ( .A(n10), .B(n11), .Z(SUM[3]) ); ND2 U7 ( .A(n12), .B(n13), .Z(SUM[4]) ); ND2 U8 ( .A(n14), .B(n15), .Z(SUM[5]) ); ND2 U9 ( .A(n16), .B(n17), .Z(SUM[1]) ); NR2 U10 ( .A(A[7]), .B(n8), .Z(n18) ); NR2 U11 ( .A(A[0]), .B(A[1]), .Z(n19) ); NR2 U12 ( .A(n16), .B(A[2]), .Z(n20) ); NR2 U13 ( .A(n6), .B(A[3]), .Z(n21) ); NR2 U14 ( .A(n10), .B(A[4]), .Z(n22) ); NR2 U15 ( .A(n12), .B(A[5]), .Z(n23) ); NR2 U16 ( .A(n14), .B(A[6]), .Z(n24) ); MUX21H U17 ( .S(n18), .A(A[8]), .B(n25), .Z(SUM[8]) ); MUX21H U18 ( .S(n24), .A(A[7]), .B(n26), .Z(SUM[7]) ); ND2 U19 ( .A(A[6]), .B(n14), .Z(n9) ); ND2 U20 ( .A(A[5]), .B(n12), .Z(n15) ); ND2 U21 ( .A(A[4]), .B(n10), .Z(n13) ); ND2 U22 ( .A(A[3]), .B(n6), .Z(n11) ); ND2 U23 ( .A(A[2]), .B(n16), .Z(n7) ); ND2 U24 ( .A(A[1]), .B(A[0]), .Z(n17) ); IV U25 ( .A(A[8]), .Z(n25) ); IV U26 ( .A(A[7]), .Z(n26) ); IV U27 ( .A(n19), .Z(n16) ); IV U28 ( .A(n21), .Z(n10) ); IV U29 ( .A(n20), .Z(n6) ); IV U30 ( .A(n23), .Z(n14) ); IV U31 ( .A(n22), .Z(n12) ); IV U32 ( .A(n24), .Z(n8) );endmodulemodule alu_DW01_add_9_3 ( A, B, CI, SUM, CO );input [8:0] A;input [8:0] B;output [8:0] SUM;input CI;output CO; wire \carry[4] , \carry[6] , \carry[2] , \carry[8] , \carry[7] , \carry[3] , \carry[5] , \carry[1] , n1, n2, n3, n4, n27, n28, n29, n30, n31; AN2 U1 ( .A(\carry[7] ), .B(A[7]), .Z(\carry[8] ) ); MUX21H U2 ( .S(\carry[7] ), .A(A[7]), .B(n1), .Z(SUM[7]) ); IV U3 ( .A(A[7]), .Z(n1) ); AN2 U4 ( .A(\carry[1] ), .B(A[1]), .Z(\carry[2] ) ); MUX21H U5 ( .S(\carry[1] ), .A(A[1]), .B(n2), .Z(SUM[1]) ); IV U6 ( .A(A[1]), .Z(n2) ); MUX21H U7 ( .S(\carry[8] ), .A(A[8]), .B(n3), .Z(SUM[8]) );
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