📄 verilog.dump
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$date May 4, 2000 18:30:43$end$version VERILOG-XL 3.0.p001$end$timescale 1ns$end$scope module system $end$var wire 1 ! VMA $end$var wire 1 " R_W $end$var parameter 32 # CYCLE $end$var reg 1 $ clock $end$var reg 1 % reset $end$var wire 8 & addr [7:0] $end$var wire 8 ' data [7:0] $end$scope module i_cpu $end$var wire 1 ( error $end$var wire 1 ) clock $end$var wire 1 * reset $end$var wire 1 ! VMA $end$var wire 1 " R_W $end$var wire 8 ' addr [7:0] $end$var wire 8 & data [7:0] $end$var wire 1 + CH [4] $end$var wire 1 , CH [3] $end$var wire 1 - CH [2] $end$var wire 1 . CH [1] $end$var wire 1 / CH [0] $end$var wire 3 0 alu_mode [2:0] $end$var wire 3 1 bus_mode [2:0] $end$var wire 1 2 carry_mode $end$var wire 1 3 S1 $end$var wire 8 4 ALU [7:0] $end$var wire 8 5 IXR [7:0] $end$var wire 8 6 IDB [7:0] $end$var wire 8 7 PC [7:0] $end$var wire 2 8 IR [1:0] $end$var wire 8 9 TDB [7:0] $end$var wire 1 : C0 $end$var wire 1 ; C1 $end$var wire 1 < C5 $end$var wire 1 = C6 $end$var wire 3 > mux_sel [2:0] $end$scope module i_pcu $end$var wire 1 ( error_in $end$var wire 3 > mux_sel [2:0] $end$var wire 1 = C6 $end$var wire 1 < C5 $end$var wire 1 ; C1 $end$var wire 8 4 ALU [7:0] $end$var wire 1 3 S1 $end$var wire 8 5 IXR [7:0] $end$var wire 1 * reset $end$var wire 8 & data [7:0] $end$var reg 8 ? PC [7:0] $end$var reg 8 @ IDR [7:0] $end$var reg 8 A IDB [7:0] $end$var reg 8 B TR [7:0] $end$var wire 8 C TDB0 [7:0] $end$var reg 8 D TDB [7:0] $end$var wire 1 E error_reset $end$upscope $end$scope module i_alub $end$var wire 2 8 IR [1:0] $end$var wire 8 6 IDB [7:0] $end$var wire 8 7 PC [7:0] $end$var wire 1 + CH [4] $end$var wire 1 , CH [3] $end$var wire 1 - CH [2] $end$var wire 1 . CH [1] $end$var wire 1 / CH [0] $end$var wire 3 0 alu_mode [2:0] $end$var wire 3 1 bus_mode [2:0] $end$var wire 1 2 carry_mode $end$var wire 1 ) clock $end$var wire 1 * reset $end$var wire 1 3 S1 $end$var wire 8 4 ALU [7:0] $end$var wire 1 ( error_out $end$var reg 8 F IXR [7:0] $end$var reg 8 G IXR_tmp [7:0] $end$var reg 8 H ACC_tmp [7:0] $end$var reg 8 I ACC [7:0] $end$var reg 1 J zero_flag $end$var reg 1 K carry_flag $end$var reg 8 L X0 [7:0] $end$var reg 8 M Y0 [7:0] $end$var wire 1 N net_1 $end$var wire 1 O net_2 $end$var wire 1 P net_3 $end$var wire 1 Q carry $end$var wire 1 R zero $end$var wire 1 S T4 $end$var wire 1 T T2 $end$var wire 1 U T3 $end$scope module i_alu $end$var wire 8 V a [7:0] $end$var wire 8 W b [7:0] $end$var wire 1 2 cin $end$var wire 3 0 sel [2:0] $end$var wire 8 4 alu_out [7:0] $end$var wire 1 Q carry $end$var wire 1 R zero $end$upscope $end$upscope $end$scope module i_ccu $end$var wire 8 9 TDB [7:0] $end$var wire 1 ) clock $end$var wire 1 * reset $end$var reg 3 X mux_sel [2:0] $end$var reg 1 Y C6 $end$var reg 1 Z C5 $end$var reg 1 [ C1 $end$var reg 1 \ C0 $end$var reg 5 ] CH [4:0] $end$var reg 3 ^ alu_mode [2:0] $end$var reg 3 _ bus_mode [2:0] $end$var reg 1 ` carry_mode $end$var reg 2 a IR [1:0] $end$var reg 6 b IR7_IR2 [5:0] $end$var wire 2 c C21_C20 [1:0] $end$var wire 8 d MAP [7:0] $end$var wire 8 e n_MA [7:0] $end$var reg 8 f MA [7:0] $end$var reg 8 g next_MA [7:0] $end$var wire 1 h n_C20 $end$var wire 1 i n_C21 $end$var wire 22 j mprom_out [21:0] $end$var reg 1 k C21 $end$var reg 1 l C20 $end$var reg 1 m C19 $end$var wire 1 n MA_carry $end$scope module i_maprom $end$var wire 6 o addr [5:0] $end$var wire 8 d dout [7:0] $end$var wire 1 p addr_error $end$upscope $end$scope module i_mprom $end$var wire 8 q addr [7:0] $end$var wire 22 j dout [21:0] $end$var wire 1 r addr_error $end$upscope $end$upscope $end$upscope $end$scope module i_pram $end$var wire 1 s clock $end$var wire 1 ! VMA $end$var wire 1 " R_W $end$var wire 8 & addr [7:0] $end$var wire 8 ' data [7:0] $end$var reg 8 t dataout [7:0] $end$upscope $end$var event 1 u reset_event $end$upscope $end$enddefinitions $end$dumpvarsx!x"b00000000000000000000000000110010 #0$1%bxxxxxxxx &bxxxxxxxx 'x(0)1*x+x,x-x.x/bxxx 0bxxx 1x2x3bxxxxxxxx 4bxxxxxxxx 5bxxxxxxxx 6bxxxxxxxx 7bxx 8bxxxxxxxx 9x:x;x<x=bxxx >bxxxxxxxx ?bxxxxxxxx @bxxxxxxxx Abxxxxxxxx Bbxxxxxxxx Cbxxxxxxxx DxEbxxxxxxxx Fbxxxxxxxx Gbxxxxxxxx Hbxxxxxxxx IxJxKbxxxxxxxx Lbxxxxxxxx MxNxOxPxQxR0S0T0Ubxxxxxxxx Vbxxxxxxxx Wbxxx XxYxZx[x\bxxxxx ]bxxx ^bxxx _x`bxx abxxxxxx bbzz cbxxxxxxxx dbzzzzzzzz ebxxxxxxxx fbxxxxxxxx gxhxibxxxxxxxxxxxxxxxxxxxxxx jxkxlxmznbxxxxxx oxpbxxxxxxxx qxr0sbxxxxxxxx txu$end#25xu0%0*0\0[b000 X0Z0Yb00000 ]b000 ^b000 _0`0m0l0kb00000000 gb00 ab000000 b0J0Kb00000000 Ib00000000 Hb00000000 Gb00000000 Bb00000000 ?b00000000 @b00000000 fb00000000 Mb00000000 A0:0;b000 >0<0=0/0.0-0,0+b000 0b000 102b00 8b000000 o0(0Nb00000000 7b00000000 qb00000000 Wb00000000 6b00000000 L0!b00000000 &b00000000 C0"130pb00000000 d0rb1111010000111011100111 jb00000000 'b00000000 V1P0h0ib00000000 Fb00000000 5#260Eb00000000 40Q1R0O#225xu1%1*#3001$1s1)#3500$0s0)b00000001 g1k1l1m1`b010 _b00010 ]1Y1Zb001 X1[1\12b010 11.1=1<b001 >1;1:b00000000 Dbzzzzzzzz &1"1!b00000000 9bzzzzzzzz Dbxxxxxxxx 'bzzzzzzzz 9bzzzzzzzz C1i1hb00000001 fb00000001 qb0101010000111001100111 j#351b00000001 40R#4001$1s1)#4500$0s0)0k0mb00011 ]b00000010 gbzz abzzzzzz bb00000010 f1/bzz 8bzzzzzz ob00000010 q030Pxpbxxxxxxxx db0000000000000000000000 jb00000001 ?b00000001 Ab00000001 7b00000001 6b00000001 Lb00000001 V0ibxxxxxxxx fbxxxxxxxx qxrbxxxxxxxxxxxxxxxxxxxxxx j#451b00000010 4#5001$1s1)#5500$0s0)bxxxxxxxx gxkxlxmx`bxxx _bxxx ^bxxxxx ]xYxZbxxx Xx[x\x2bxxx 1bxxx 0x/x.x-x,x+x=x<bxxx >x;x:b00000010 Bbzzzzzzzz @b00000000 Ax3bxxxxxxxx &bxxxxxxxx Cx"x!b00000000 6b00000000 LxPb00000000 Vxixh#551bxxxxxxxx 4xQxRxO#6001$1s1)xTxUxSxJxKbxxxxxxxx IxNx(bxxxxxxxx Fbxxxxxxxx 5#601xE#6500$0s0)bxxxxxxxx Hbxxxxxxxx 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