class.ptf

altera_avalon,welcome to download

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#:-: file: class.ptf
#:-: date: 2001.11.13 15:43:54
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# class.ptf
# for SOPC library component: altera_avalon_cs8900
# 
# This PTF-file describes the interface to an
# external ethernet PHY/MAC chip: The Cirrus Logic
# "CrystalLAN" CS8900.  This chip is
# commonly distributed as part of the Altera "Nios Ethernet
# Development Kit."   The chip features an ISA-bus interface,
# and can be accessed in either "Memory" or "IO" mode.
# 
# This file packages an interface to this chip as an
# SOPC "component" that you can add to your system.
# 
# The interface only allows IO-mode access to the CS8900 chip.
# There no board-level hardware stopping you from using the chip in
# memory-mode, but this particular library component does not.
# 
# This is a pretty standard component, except for one thing:
# it doesn't have a chip-select signal.  This is because the CS8900
# (in IO mode) doesn't use a chip-select.  Instead, its read_n- and
# write_n-strobe inputs are only active when it is being accessed.
# The read_n and write_n outputs produced by this interface have that
# characteristic, as do all Avalon read_n/write_n-type ports which
# include setup/hold times.
# 
# H O W    T O   H O O K   U P   Y O U R   C H I P
# 
# This table summarizes the connections you need to make between
# this interface and your CS8900 chip to make it work
# (power supply pins omitted for clarity).  This assumes you are
# using a 10base-T network interface, and not an "AUI" interface.
# 
# Chip pin   |               Connect to
# -------------+-----------------------------------------------
# INTRQ0     |  irq         input to this interface.
# SD[15..0]  |  data        bus of this interface.
# IOR_n      |  ior_n       output from this interface.
# IOW_n      |  iow_n       output from this interface.
# SBHE_n     |  bytenablen  bus of this interface, bit 1.
# SA[3,2,1]  |  address "   bus of this interface, bits 4, 3, and 2(!)
# SA[19..10] |  GND         (tie low)
# SA[9,8]    |  +3.3V       (tie high) Chip works when it sees addr "0x300".
# SA[0]      |  GNDp         (tie low)
# RESET      |  reset       NOT on this interface: inverted version
# |                of system's "reset_n" signal.
# |
# XTAL1      |  20MHz       Oscillator-output
# RXD-       |  RXDM        On Ethernet magnetics/connector.
# RXD+       |  RXDP        On Ethernet magnetics/connector.
# TXD-       |  TXDM        On Ethernet magnetics/connector.
# TXD+       |  TXDP        On Ethernet magnetics/connector.
# LINKLED_n  |  "link"      LED drive.
# LANLED_n   |  "lan"       LED drive.
# |
# MEMW_n     |  +3.3V       (tie high)
# MEMR_n     |  +3.3V       (tie high)
# REFRESH_n  |  +3.3V       (tie high through pullup resistor)
# MEMCS16_n  |  +3.3V       (tie high through pullup resistor)
# IOCS16_n   |  +3.3V       (tie high through pullup resistor)
# IOCHRDY    |  +3.3V       (tie high through pullup resistor)
# AEN        |  GND         (tie low trhough pull-down resistor)
# CHIPSEL_n  |  GND         (tie low trhough pull-down resistor)
# EEDATAIN   |  GND         (tie low)
# ELCS       |  GND         (tie low)
# XTAL2      |  N/C
# INTRQ1     |  N/C
# INTRQ2     |  N/C
# INTRQ3     |  N/C
# DMARQ0     |  N/C
# DMARQ1     |  N/C
# DMARQ2     |  N/C
# DMACK0     |  N/C
# DMACK1     |  N/C
# DMACK2     |  N/C
# HWSLEEP    |  N/C
# TESTSEL    |  N/C
# EESK       |  N/C
# EEDATAOUT  |  N/C
# EECS       |  N/C
# CSOUT      |  N/C
# DO-        |  N/C
# DO+        |  N/C
# DI-        |  N/C
# DI+        |  N/C
# CI-        |  N/C
# CI+        |  N/C
   CLASS altera_avalon_cs8900
   {
      SDK_GENERATION
      {
         SDK_FILES all
         {
            sdk_files_dir = "sdk";
            sdk_files_list = "
                                    lib/cs8900.c
                                    inc/cs8900.h
                                    src/hello_cs8900.c
                           ";
         }
      }
      ASSOCIATED_FILES 
      {
         # No generator program, because this is a system-external component:
         Generator_Program = "--none--";
      }
      USER_INTERFACE 
      {
         USER_LABELS 
         {
            name = "CS8900 Interface (Ethernet)";
            description = "Nios Ethernet Development Kit 1.x Daughtercard<br>10Mb Speed, 16-bit Interface";
            technology = "Ethernet";
            license = "full";
         }
         LINKS
         {
            LINK help
            {
                title = "Nios Ethernet Development Kit User Guide";
                url = "http://www.altera.com/literature/ug/ug_niosedk.pdf";
            }
            LINK plugs
            { 
               title="Plugs Ethernet Library";
               url="http://www.altera.com/literature/manual/mnl_plugs.pdf";
            }
         }
      }
      MODULE_DEFAULTS 
      {
         class = "altera_avalon_cs8900";
         class_version = "5.1";
         WIZARD_SCRIPT_ARGUMENTS 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Wire_Test_Bench_Values = "1";
            Instantiate_In_System_Module = "0";
            Is_Enabled = "1";
            Top_Level_Ports_Are_Enumerated = "1";
         }
         SLAVE s1
         {
            SYSTEM_BUILDER_INFO 
            {
               Bus_Type = "avalon_tristate";
               Uses_Tri_State_Data_Bus = "1";
               Address_Alignment = "native";
               Address_Width = "3";
               Data_Width = "16";
               Has_IRQ = "1";
               Read_Wait_States = "5";
               Write_Wait_States = "5";
               Setup_Time = "1";
               Hold_Time = "1";
               Is_Memory_Device = "0";
               Date_Modified = "2001.10.9.10:51:51";
               IRQ_Number = "--unknown--";
               Base_Address = "--unknown--";
               Tri_State_Data_Bus = "--unknown--";
            }
            PORT_WIRING 
            {
               PORT irq
               {
                  direction = "output";
                  width = "1";
                  type = "irq";
                  test_bench_value = "0";
               }
               PORT byteenablen
               {
                  is_shared = "1";
                  direction = "input";
                  width = "2";
                  type = "byteenable_n";
               }
               PORT address
               {
                  is_shared = "1";
                  direction = "input";
                  width = "3";
                  type = "address";
               }
               PORT data
               {
                  is_shared = "1";
                  direction = "inout";
                  width = "16";
                  type = "data";
               }
               PORT iow_n
               {
                  direction = "input";
                  width = "1";
                  type = "write_n";
               }
               PORT ior_n
               {
                  direction = "input";
                  width = "1";
                  type = "read_n";
               }
            }
         }
      }
   }