📄 led.lis
字号:
.module led.c
.area data(ram, con, rel)
0000 _T0Count0::
0000 .blkb 2
.area idata
0000 0000 .word 0
.area data(ram, con, rel)
0002 .dbfile d:\excersize\led.h
0002 .dbsym e T0Count0 _T0Count0 i
.area text(rom, con, rel)
0000 .dbfile d:\excersize\led.h
0000 .dbfile D:\excersize\led.c
0000 .dbfunc e port_init _port_init fV
.even
0000 _port_init::
0000 .dbline -1
0000 .dbline 9
0000 ; //ICC-AVR application builder : 2006-5-22 9:26:54
0000 ; // Target : M128
0000 ; // Crystal: 16.000Mhz
0000 ;
0000 ; #include <iom128v.h>
0000 ; #include <macros.h>
0000 ; #include <d:\excersize\led.h>
0000 ; void port_init(void)
0000 ; {
0000 .dbline 10
0000 ; PORTA = 0x00;
0000 2224 clr R2
0002 2BBA out 0x1b,R2
0004 .dbline 11
0004 ; DDRA = 0x00;
0004 2ABA out 0x1a,R2
0006 .dbline 12
0006 ; PORTB = 0xFF;
0006 8FEF ldi R24,255
0008 88BB out 0x18,R24
000A .dbline 13
000A ; DDRB = 0xFF;
000A 87BB out 0x17,R24
000C .dbline 14
000C ; PORTC = 0x00; //m103 output only
000C 25BA out 0x15,R2
000E .dbline 15
000E ; DDRC = 0xFF;
000E 84BB out 0x14,R24
0010 .dbline 16
0010 ; PORTD = 0xFF;
0010 82BB out 0x12,R24
0012 .dbline 17
0012 ; DDRD = 0xF0;
0012 80EF ldi R24,240
0014 81BB out 0x11,R24
0016 .dbline 18
0016 ; PORTE = 0x00;
0016 23B8 out 0x3,R2
0018 .dbline 19
0018 ; DDRE = 0x00;
0018 22B8 out 0x2,R2
001A .dbline 20
001A ; PORTF = 0x00;
001A 20926200 sts 98,R2
001E .dbline 21
001E ; DDRF = 0x00;
001E 20926100 sts 97,R2
0022 .dbline 22
0022 ; PORTG = 0x00;
0022 20926500 sts 101,R2
0026 .dbline 23
0026 ; DDRG = 0x00;
0026 20926400 sts 100,R2
002A .dbline -2
002A L1:
002A .dbline 0 ; func end
002A 0895 ret
002C .dbend
002C .dbfunc e watchdog_init _watchdog_init fV
.even
002C _watchdog_init::
002C .dbline -1
002C .dbline 26
002C ; }
002C ; void watchdog_init(void)
002C ; {
002C .dbline 27
002C ; WDR(); //this prevents a timout on enabling//
002C A895 wdr
002E .dbline 28
002E ; WDTCR = 0x0F; //WATCHDOG ENABLED - dont forget to issue WDRs
002E 8FE0 ldi R24,15
0030 81BD out 0x21,R24
0032 .dbline -2
0032 L2:
0032 .dbline 0 ; func end
0032 0895 ret
0034 .dbend
0034 .dbfunc e timer0_init _timer0_init fV
.even
0034 _timer0_init::
0034 .dbline -1
0034 .dbline 30
0034 ; }
0034 ; void timer0_init(void){
0034 .dbline 31
0034 ; TCCR0 = 0x00; //stop
0034 2224 clr R2
0036 23BE out 0x33,R2
0038 .dbline 32
0038 ; ASSR = 0x00; //set async mode//同步方式，允许更新计数，比较输出，控制寄存器
0038 20BE out 0x30,R2
003A .dbline 33
003A ; TCNT0 = 0x83; //set count
003A 83E8 ldi R24,131
003C 82BF out 0x32,R24
003E .dbline 34
003E ; OCR0 = 0x7D;
003E 8DE7 ldi R24,125
0040 81BF out 0x31,R24
0042 .dbline 35
0042 ; TCCR0 = 0x05; //start timer//128分频
0042 85E0 ldi R24,5
0044 83BF out 0x33,R24
0046 .dbline -2
0046 L3:
0046 .dbline 0 ; func end
0046 0895 ret
0048 .dbend
.area vector(rom, abs)
.org 60
003C 0C942400 jmp _timer0_comp_isr
.area text(rom, con, rel)
0048 .dbfile D:\excersize\led.c
0048 .dbfunc e timer0_comp_isr _timer0_comp_isr fV
.even
0048 _timer0_comp_isr::
0048 8A93 st -y,R24
004A 9A93 st -y,R25
004C 8FB7 in R24,0x3f
004E 8A93 st -y,R24
0050 .dbline -1
0050 .dbline 39
0050 ; }
0050 ; //======================================================time0 中断
0050 ; #pragma interrupt_handler timer0_comp_isr:16
0050 ; void timer0_comp_isr(void){
0050 .dbline 40
0050 ; TCNT0 = 0x83;
0050 83E8 ldi R24,131
0052 82BF out 0x32,R24
0054 .dbline 41
0054 ; T0Count0++;
0054 80910000 lds R24,_T0Count0
0058 90910100 lds R25,_T0Count0+1
005C 0196 adiw R24,1
005E 90930100 sts _T0Count0+1,R25
0062 80930000 sts _T0Count0,R24
0066 .dbline -2
0066 L4:
0066 8991 ld R24,y+
0068 8FBF out 0x3f,R24
006A 9991 ld R25,y+
006C 8991 ld R24,y+
006E .dbline 0 ; func end
006E 1895 reti
0070 .dbend
0070 .dbfunc e delay _delay fV
0070 ; j -> R16,R17
0070 ; i -> R18,R19
.even
0070 _delay::
0070 .dbline -1
0070 .dbline 47
0070 ;
0070 ; //compare occured TCNT0=OCR0
0070 ; }
0070 ; //call this routine to initialize all peripherals
0070 ; void delay(void)
0070 ; {
0070 .dbline 49
0070 ;
0070 ; UI i=0;
0070 2227 clr R18
0072 3327 clr R19
0074 .dbline 50
0074 ; UI j=0;
0074 0027 clr R16
0076 1127 clr R17
0078 .dbline 51
0078 ; for(j=0;j<500;j++)
0078 0CC0 xjmp L9
007A L6:
007A .dbline 52
007A ; {
007A .dbline 53
007A ; WDR();
007A A895 wdr
007C .dbline 54
007C 2227 clr R18
007E 3327 clr R19
0080 02C0 xjmp L13
0082 L10:
0082 .dbline 54
0082 L11:
0082 .dbline 54
0082 2F5F subi R18,255 ; offset = 1
0084 3F4F sbci R19,255
0086 L13:
0086 .dbline 54
0086 2838 cpi R18,136
0088 E3E1 ldi R30,19
008A 3E07 cpc R19,R30
008C D0F3 brlo L10
008E .dbline 55
008E L7:
008E .dbline 51
008E 0F5F subi R16,255 ; offset = 1
0090 1F4F sbci R17,255
0092 L9:
0092 .dbline 51
0092 043F cpi R16,244
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