📄 oput.lis
字号:
0000 ; {
0000 .dbline 13
0000 ; asm(
.area memory(abs)
.org 0xD000
D000 _CAN0Addr:: .blkb 50
.org 0xE000
E000 _CAN1Addr:: .blkb 50
.org 0xF000
F000 _IOAddr:: .blkb 50
.text
0000 .dbline -2
0000 L1:
0000 .dbline 0 ; func end
0000 0895 ret
0002 .dbend
0002 .dbfunc e port_init _port_init fV
.even
0002 _port_init::
0002 .dbline -1
0002 .dbline 26
0002 ; ".area memory(abs)\n"
0002 ; ".org 0xD000\n"
0002 ; " _CAN0Addr:: .blkb 50\n"
0002 ; ".org 0xE000\n"
0002 ; " _CAN1Addr:: .blkb 50\n"
0002 ; ".org 0xF000\n"
0002 ; " _IOAddr:: .blkb 50\n"
0002 ; ".text\n"
0002 ; );
0002 ; }
0002 ; //======================================================控制器IO口定义
0002 ; void port_init(void)
0002 ; {
0002 .dbline 27
0002 ; PORTA = 0x00;
0002 2224 clr R2
0004 2BBA out 0x1b,R2
0006 .dbline 28
0006 ; DDRA = 0x00;
0006 2ABA out 0x1a,R2
0008 .dbline 29
0008 ; PORTB = 0xFF;
0008 8FEF ldi R24,255
000A 88BB out 0x18,R24
000C .dbline 30
000C ; DDRB = 0xFF;
000C 87BB out 0x17,R24
000E .dbline 31
000E ; PORTC = 0xFF; //m103 output only
000E 85BB out 0x15,R24
0010 .dbline 32
0010 ; DDRC = 0xFF;
0010 84BB out 0x14,R24
0012 .dbline 33
0012 ; PORTD = 0xFF;
0012 82BB out 0x12,R24
0014 .dbline 34
0014 ; DDRD = 0xF0;
0014 80EF ldi R24,240
0016 81BB out 0x11,R24
0018 .dbline 35
0018 ; PORTE = 0xFF;
0018 8FEF ldi R24,255
001A 83B9 out 0x3,R24
001C .dbline 36
001C ; DDRE = 0x08;
001C 88E0 ldi R24,8
001E 82B9 out 0x2,R24
0020 .dbline 37
0020 ; PORTF = 0xFC;
0020 8CEF ldi R24,252
0022 80936200 sts 98,R24
0026 .dbline 38
0026 ; DDRF = 0x0C;
0026 8CE0 ldi R24,12
0028 80936100 sts 97,R24
002C .dbline 39
002C ; PORTG = 0x1F;
002C 8FE1 ldi R24,31
002E 80936500 sts 101,R24
0032 .dbline 40
0032 ; DDRG = 0x00;
0032 20926400 sts 100,R2
0036 .dbline -2
0036 L2:
0036 .dbline 0 ; func end
0036 0895 ret
0038 .dbend
0038 .dbfunc e watchdog_init _watchdog_init fV
.even
0038 _watchdog_init::
0038 .dbline -1
0038 .dbline 46
0038 ; }
0038 ; //======================================================内部看门狗初始化
0038 ; //Watchdog initialisation
0038 ; // prescale: 2048K cycles
0038 ; void watchdog_init(void)
0038 ; {
0038 .dbline 47
0038 ; WDR(); //this prevents a timout on enabling//
0038 A895 wdr
003A .dbline 48
003A ; WDTCR = 0x0F; //WATCHDOG ENABLED - dont forget to issue WDRs
003A 8FE0 ldi R24,15
003C 81BD out 0x21,R24
003E .dbline -2
003E L3:
003E .dbline 0 ; func end
003E 0895 ret
0040 .dbend
0040 .dbfunc e uart0_init _uart0_init fV
.even
0040 _uart0_init::
0040 .dbline -1
0040 .dbline 60
0040 ; }
0040 ;
0040 ;
0040 ; //======================================================串口初始化
0040 ; //UART0 initialisation
0040 ; // desired baud rate:38400
0040 ; // actual baud rate:38462 (0.2%)
0040 ; // char size: 8 bit
0040 ; // parity: Disabled
0040 ;
0040 ; void uart0_init(void)
0040 ; {
0040 .dbline 61
0040 ; UCSR0B = 0x00; //disable while setting baud rate
0040 2224 clr R2
0042 2AB8 out 0xa,R2
0044 .dbline 62
0044 ; UCSR0A = 0x00;
0044 2BB8 out 0xb,R2
0046 .dbline 63
0046 ; UCSR0C = 0x06;
0046 86E0 ldi R24,6
0048 80939500 sts 149,R24
004C .dbline 64
004C ; UBRR0L = 0x19; //set baud rate lo
004C 89E1 ldi R24,25
004E 89B9 out 0x9,R24
0050 .dbline 65
0050 ; UBRR0H = 0x00; //set baud rate hi
0050 20929000 sts 144,R2
0054 .dbline 66
0054 ; UCSR0B = 0xB8;
0054 88EB ldi R24,184
0056 8AB9 out 0xa,R24
0058 .dbline -2
0058 L4:
0058 .dbline 0 ; func end
0058 0895 ret
005A .dbend
.area vector(rom, abs)
.org 76
004C 0C942D00 jmp _uart0_udre_isr
.area text(rom, con, rel)
005A .dbfile D:\excersize\oput.c
005A .dbfunc e uart0_udre_isr _uart0_udre_isr fV
.even
005A _uart0_udre_isr::
005A 2A92 st -y,R2
005C 3A92 st -y,R3
005E 8A93 st -y,R24
0060 9A93 st -y,R25
0062 EA93 st -y,R30
0064 FA93 st -y,R31
0066 2FB6 in R2,0x3f
0068 2A92 st -y,R2
006A .dbline -1
006A .dbline 72
006A ; }
006A ;
006A ;
006A ; //======================================================串口0发送中断
006A ; #pragma interrupt_handler uart0_udre_isr:20
006A ; void uart0_udre_isr(void){
006A .dbline 73
006A ; if(TxOperateSp0!=TxLoadSp0){
006A 20900000 lds R2,_TxLoadSp0
006E 30900100 lds R3,_TxOperateSp0
0072 3214 cp R3,R2
0074 71F0 breq L6
0076 .dbline 73
0076 .dbline 74
0076 ; UDR0=TxBuffer0[TxLoadSp0++];
0076 3324 clr R3
0078 822D mov R24,R2
007A 8F5F subi R24,255 ; addi 1
007C 80930000 sts _TxLoadSp0,R24
0080 80E0 ldi R24,<_TxBuffer0
0082 90E0 ldi R25,>_TxBuffer0
0084 E22D mov R30,R2
0086 FF27 clr R31
0088 E80F add R30,R24
008A F91F adc R31,R25
008C 2080 ldd R2,z+0
008E 2CB8 out 0xc,R2
0090 .dbline 75
0090 ; }
0090 03C0 xjmp L7
0092 L6:
0092 .dbline 76
0092 .dbline 76
0092 8AB1 in R24,0xa
0094 8F7D andi R24,223
0096 8AB9 out 0xa,R24
0098 .dbline 76
0098 L7:
0098 .dbline -2
0098 L5:
0098 2990 ld R2,y+
009A 2FBE out 0x3f,R2
009C F991 ld R31,y+
009E E991 ld R30,y+
00A0 9991 ld R25,y+
00A2 8991 ld R24,y+
00A4 3990 ld R3,y+
00A6 2990 ld R2,y+
00A8 .dbline 0 ; func end
00A8 1895 reti
00AA .dbend
00AA .dbfunc e timer0_init _timer0_init fV
.even
00AA _timer0_init::
00AA .dbline -1
00AA .dbline 86
00AA ; else{UCSR0B&=0XDF;}
00AA ;
00AA ; }
00AA ;
00AA ;
00AA ; //======================================================time0 初始化
00AA ; //TIMER0 initialisation - prescale:32
00AA ; // WGM: Normal
00AA ; // desired value: 1KHz
00AA ; // actual value: 1.000KHz (0.0%)
00AA ; void timer0_init(void){
00AA .dbline 87
00AA ; TCCR0 = 0x00; //stop
00AA 2224 clr R2
00AC 23BE out 0x33,R2
00AE .dbline 88
00AE ; ASSR = 0x00; //set async mode//同步方式，允许更新计数，比较输出，控制寄存器
00AE 20BE out 0x30,R2
00B0 .dbline 89
00B0 ; TCNT0 = 0x83; //set count
00B0 83E8 ldi R24,131
00B2 82BF out 0x32,R24
00B4 .dbline 90
00B4 ; OCR0 = 0x7D;
00B4 8DE7 ldi R24,125
00B6 81BF out 0x31,R24
00B8 .dbline 91
00B8 ; TCCR0 = 0x05; //start timer//128分频
00B8 85E0 ldi R24,5
00BA 83BF out 0x33,R24
00BC .dbline -2
00BC L8:
00BC .dbline 0 ; func end
00BC 0895 ret
00BE .dbend
.area vector(rom, abs)
.org 60
003C 0C945F00 jmp _timer0_comp_isr
.area text(rom, con, rel)
00BE .dbfile D:\excersize\oput.c
00BE .dbfunc e timer0_comp_isr _timer0_comp_isr fV
.even
00BE _timer0_comp_isr::
00BE 8A93 st -y,R24
00C0 9A93 st -y,R25
00C2 8FB7 in R24,0x3f
00C4 8A93 st -y,R24
00C6 .dbline -1
00C6 .dbline 95
00C6 ; }
00C6 ; //======================================================time0 中断
00C6 ; #pragma interrupt_handler timer0_comp_isr:16
00C6 ; void timer0_comp_isr(void){
00C6 .dbline 96
00C6 ; TCNT0 = 0x83;
00C6 83E8 ldi R24,131
00C8 82BF out 0x32,R24
00CA .dbline 97
00CA ; T0Count0++;
00CA 80910B00 lds R24,_T0Count0
00CE 90910C00 lds R25,_T0Count0+1
00D2 0196 adiw R24,1
00D4 90930C00 sts _T0Count0+1,R25
00D8 80930B00 sts _T0Count0,R24
00DC .dbline 98
00DC ; T0Count1++;
00DC 80910D00 lds R24,_T0Count1
00E0 90910E00 lds R25,_T0Count1+1
00E4 0196 adiw R24,1
00E6 90930E00 sts _T0Count1+1,R25
00EA 80930D00 sts _T0Count1,R24
00EE .dbline 99
00EE ; T0Count2++;
00EE 80910F00 lds R24,_T0Count2
00F2 90911000 lds R25,_T0Count2+1
00F6 0196 adiw R24,1
00F8 90931000 sts _T0Count2+1,R25
00FC 80930F00 sts _T0Count2,R24
0100 .dbline 100
0100 ; T0Count3++;
0100 80911100 lds R24,_T0Count3
0104 90911200 lds R25,_T0Count3+1
0108 0196 adiw R24,1
010A 90931200 sts _T0Count3+1,R25
010E 80931100 sts _T0Count3,R24
0112 .dbline 101
0112 ; T0Count4++;
0112 80911300 lds R24,_T0Count4
0116 90911400 lds R25,_T0Count4+1
011A 0196 adiw R24,1
011C 90931400 sts _T0Count4+1,R25
0120 80931300 sts _T0Count4,R24
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