oput.s

avr单片机

	std z+0,R24
	.dbline -2
L27:
	xcall pop_gset3
	.dbline 0 ; func end
	ret
	.dbsym r head 22 c
	.dbsym r j 10 c
	.dbsym r i 20 c
	.dbend
	.dbfunc e io_test _io_test fV
;          Delay -> R20,R21
;              i -> R22
	.even
_io_test::
	xcall push_gset2
	.dbline -1
	.dbline 187
; }
; 
; 
; 					   														   										
; void io_test(void){
	.dbline 188
;    UC i=0;
	clr R22
	.dbline 190
;    UI Delay;
;    if(T0Count4>500){//||(RxFlag==ON)){
	ldi R24,500
	ldi R25,1
	lds R2,_T0Count4
	lds R3,_T0Count4+1
	cp R24,R2
	cpc R25,R3
	brlo X0
	xjmp L34
X0:
	.dbline 190
	.dbline 191
;       T0Count4=0;
	clr R2
	clr R3
	sts _T0Count4+1,R3
	sts _T0Count4,R2
	.dbline 193
; //	  RxFlag=OFF;  
;       OutputByte0Reg=OutputTable[TestIOSp][0];
	lds R2,_TestIOSp
	ldi R24,3
	mul R24,R2
	movw R30,R0
	ldi R24,<_OutputTable
	ldi R25,>_OutputTable
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	sts _OutputByte0Reg,R2
	.dbline 194
;       OutputByte1Reg=OutputTable[TestIOSp][1];
	lds R2,_TestIOSp
	ldi R24,3
	mul R24,R2
	movw R30,R0
	ldi R24,<_OutputTable+1
	ldi R25,>_OutputTable+1
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	sts _OutputByte1Reg,R2
	.dbline 195
;       OutputByte2Reg=OutputTable[TestIOSp][2];
	lds R2,_TestIOSp
	ldi R24,3
	mul R24,R2
	movw R30,R0
	ldi R24,<_OutputTable+2
	ldi R25,>_OutputTable+2
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	sts _OutputByte2Reg,R2
	.dbline 197
;    
;       IOAddr[OutputByte0]=OutputByte0Reg;
	lds R2,_OutputByte0Reg
	sts _IOAddr+4,R2
	.dbline 198
;       IOAddr[OutputByte1]=OutputByte1Reg;
	lds R2,_OutputByte1Reg
	sts _IOAddr+5,R2
	.dbline 199
;       IOAddr[OutputByte2]=OutputByte2Reg;
	lds R2,_OutputByte2Reg
	sts _IOAddr+6,R2
	.dbline 201
	clr R20
	clr R21
	xjmp L44
L41:
	.dbline 201
L42:
	.dbline 201
	subi R20,255  ; offset = 1
	sbci R21,255
L44:
	.dbline 201
;    
;       for(Delay=0;Delay<5000;Delay++);
	cpi R20,136
	ldi R30,19
	cpc R21,R30
	brlo L41
	xjmp L46
L45:
	.dbline 203
;    
;       while(i<5){
	.dbline 204
;          if(InputByte0Reg==IOAddr[InputByte0])i++;
	lds R2,_IOAddr
	lds R3,_InputByte0Reg
	cp R3,R2
	brne L48
	.dbline 204
	inc R22
	xjmp L49
L48:
	.dbline 205
;          else {InputByte0Reg=IOAddr[InputByte0];i=0;}
	.dbline 205
	lds R2,_IOAddr
	sts _InputByte0Reg,R2
	.dbline 205
	clr R22
	.dbline 205
L49:
	.dbline 206
L46:
	.dbline 203
	cpi R22,5
	brlo L45
	.dbline 207
;       }
;       i=0;
	clr R22
	xjmp L51
L50:
	.dbline 208
;       while(i<5){
	.dbline 209
;          if(InputByte1Reg==IOAddr[InputByte1])i++;
	lds R2,_IOAddr+1
	lds R3,_InputByte1Reg
	cp R3,R2
	brne L53
	.dbline 209
	inc R22
	xjmp L54
L53:
	.dbline 210
;          else {InputByte1Reg=IOAddr[InputByte1];i=0;}
	.dbline 210
	lds R2,_IOAddr+1
	sts _InputByte1Reg,R2
	.dbline 210
	clr R22
	.dbline 210
L54:
	.dbline 211
L51:
	.dbline 208
	cpi R22,5
	brlo L50
	.dbline 212
;       }
;       i=0;
	clr R22
	xjmp L58
L57:
	.dbline 213
;       while(i<5){
	.dbline 214
;       if(InputByte2Reg==IOAddr[InputByte2])i++;
	lds R2,_IOAddr+2
	lds R3,_InputByte2Reg
	cp R3,R2
	brne L60
	.dbline 214
	inc R22
	xjmp L61
L60:
	.dbline 215
;          else {InputByte2Reg=IOAddr[InputByte2];i=0;}
	.dbline 215
	lds R2,_IOAddr+2
	sts _InputByte2Reg,R2
	.dbline 215
	clr R22
	.dbline 215
L61:
	.dbline 216
L58:
	.dbline 213
	cpi R22,5
	brlo L57
	.dbline 217
;       }
;       i=0;
	clr R22
	xjmp L65
L64:
	.dbline 218
;       while(i<5){
	.dbline 219
;       if(InputByte3Reg==IOAddr[InputByte3])i++;
	lds R2,_IOAddr+3
	lds R3,_InputByte3Reg
	cp R3,R2
	brne L67
	.dbline 219
	inc R22
	xjmp L68
L67:
	.dbline 220
;          else {InputByte3Reg=IOAddr[InputByte3];i=0;}
	.dbline 220
	lds R2,_IOAddr+3
	sts _InputByte3Reg,R2
	.dbline 220
	clr R22
	.dbline 220
L68:
	.dbline 221
L65:
	.dbline 218
	cpi R22,5
	brlo L64
	.dbline 222
;       }
;       i=0;
	clr R22
	.dbline 223
;       TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 224
;   tx0_uc_to_bcd(OutputByte0Reg);
	lds R16,_OutputByte0Reg
	xcall _tx0_uc_to_bcd
	.dbline 225
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 226
;   tx0_uc_to_bcd(OutputByte1Reg);
	lds R16,_OutputByte1Reg
	xcall _tx0_uc_to_bcd
	.dbline 227
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 228
;   tx0_uc_to_bcd(OutputByte2Reg);
	lds R16,_OutputByte2Reg
	xcall _tx0_uc_to_bcd
	.dbline 229
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 230
;   tx0_uc_to_bcd(InputByte0Reg);
	lds R16,_InputByte0Reg
	xcall _tx0_uc_to_bcd
	.dbline 231
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 232
;   tx0_uc_to_bcd(InputByte1Reg);
	lds R16,_InputByte1Reg
	xcall _tx0_uc_to_bcd
	.dbline 233
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 234
;   tx0_uc_to_bcd(InputByte2Reg);
	lds R16,_InputByte2Reg
	xcall _tx0_uc_to_bcd
	.dbline 235
;   TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 236
;   tx0_uc_to_bcd(InputByte3Reg);
	lds R16,_InputByte3Reg
	xcall _tx0_uc_to_bcd
	.dbline 243
;      // if(InputByte0Reg!=InputTable[TestIOSp][0])IOErrorFlag=ON;
;      // else if(InputByte1Reg!=InputTable[TestIOSp][1])IOErrorFlag=ON;
;       //else if(InputByte2Reg!=InputTable[TestIOSp][2])IOErrorFlag=ON;
;       //else if(InputByte3Reg!=InputTable[TestIOSp][3])IOErrorFlag=ON;
; 	  //else IOErrorFlag=OFF;
; 	 // tx0_operate();
; 	 if(InputByte0Reg==InputTable[TestIOSp][0]&& InputByte1Reg==InputTable[TestIOSp][1]
	lds R2,_TestIOSp
	ldi R24,4
	mul R24,R2
	ldi R24,<_InputTable
	ldi R25,>_InputTable
	movw R30,R0
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	lds R3,_InputByte0Reg
	cp R3,R2
	breq X1
	xjmp L71
X1:
	ldi R24,<_InputTable+1
	ldi R25,>_InputTable+1
	movw R30,R0
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	lds R3,_InputByte1Reg
	cp R3,R2
	breq X2
	xjmp L71
X2:
	ldi R24,<_InputTable+2
	ldi R25,>_InputTable+2
	movw R30,R0
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	lds R3,_InputByte2Reg
	cp R3,R2
	breq X3
	xjmp L71
X3:
	ldi R24,<_InputTable+3
	ldi R25,>_InputTable+3
	movw R30,R0
	add R30,R24
	adc R31,R25
	ldd R2,z+0
	lds R3,_InputByte3Reg
	cp R3,R2
	breq X4
	xjmp L71
X4:
	.dbline 245
;    && InputByte2Reg==InputTable[TestIOSp][2] && InputByte3Reg==InputTable[TestIOSp][3])
;    {
	.dbline 247
;     // IOErrorFlag=0;
; 	 PORTB=0xFF;
	ldi R24,255
	out 0x18,R24
	.dbline 248
; 	 TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 249
; 	 tx0_uc_to_bcd(TestIOSp);
	lds R16,_TestIOSp
	xcall _tx0_uc_to_bcd
	.dbline 250
; 	 TxBuffer0[TxOperateSp0++]= 'O';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,79
	std z+0,R24
	.dbline 251
; 	 TxBuffer0[TxOperateSp0++]= 'k';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,107
	std z+0,R24
	.dbline 252
; 	 TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 253
; 	 UCSR0B|=0X20;
	sbi 0xa,5
	.dbline 255
; 	 
; 	}
	xjmp L72
L71:
	.dbline 257
;    else 
;    {
	.dbline 259
;     //IOErrorFlag=1;
; 	PORTB=0x00;
	clr R2
	out 0x18,R2
	.dbline 260
; 	TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 261
; 	tx0_uc_to_bcd(TestIOSp);
	lds R16,_TestIOSp
	xcall _tx0_uc_to_bcd
	.dbline 262
; 	TxBuffer0[TxOperateSp0++]= 'E';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,69
	std z+0,R24
	.dbline 263
; 	TxBuffer0[TxOperateSp0++]= 'r';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,114
	std z+0,R24
	.dbline 264
; 	TxBuffer0[TxOperateSp0++]= 'r';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,114
	std z+0,R24
	.dbline 265
; 	TxBuffer0[TxOperateSp0++]= 'O';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,79
	std z+0,R24
	.dbline 266
; 	TxBuffer0[TxOperateSp0++]= 'r';
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,114
	std z+0,R24
	.dbline 267
; 	TxBuffer0[TxOperateSp0++]=0x20;
	lds R2,_TxOperateSp0
	clr R3
	mov R24,R2
	subi R24,255    ; addi 1
	sts _TxOperateSp0,R24
	ldi R24,<_TxBuffer0
	ldi R25,>_TxBuffer0
	mov R30,R2
	clr R31
	add R30,R24
	adc R31,R25
	ldi R24,32
	std z+0,R24
	.dbline 268
; 	UCSR0B|=0X20;
	sbi 0xa,5
	.dbline 269
;     }
L72:
	.dbline 270
	lds R24,_TestIOSp
	subi R24,255    ; addi 1
	sts _TestIOSp,R24
	.dbline 270
	andi R24,15
	sts _TestIOSp,R24
	.dbline 271
L34:
	.dbline -2
L33:
	xcall pop_gset2
	.dbline 0 ; func end
	ret
	.dbsym r Delay 20 i
	.dbsym r i 22 c
	.dbend
	.dbfunc e main _main fV
	.even
_main::
	.dbline -1
	.dbline 275
; 	TestIOSp++;TestIOSp&=0x0F;
;   }
; 
; } 
; //===============================================主程序
; void main(void){
	.dbline 276
;    WatchDog();
	xcall _WatchDog
	.dbline 277
;    watchdog_init();
	xcall _watchdog_init
	.dbline 278
;    init_devices();
	xcall _init_devices
	.dbline 280
;    //can_init(); 
;    set_value();
	xcall _set_value
	xjmp L78
L77:
	.dbline 281
	.dbline 282
	xcall _io_test
	.dbline 283
	xcall _WatchDog
	.dbline 293
L78:
	.dbline 281
	xjmp L77
X5:
	.dbline -2
L76:
	.dbline 0 ; func end
	ret
	.dbend
	.area bss(ram, con, rel)
	.dbfile D:\excersize\oput.c
_CanTxBuffer1::
	.blkb 104
	.dbfile D:\kcb\kcbtest1.h
	.dbsym e CanTxBuffer1 _CanTxBuffer1 A[104:8:13]c
_CanTxBuffer0::
	.blkb 104
	.dbsym e CanTxBuffer0 _CanTxBuffer0 A[104:8:13]c
_CanRxBuffer1::
	.blkb 104
	.dbsym e CanRxBuffer1 _CanRxBuffer1 A[104:8:13]c
_CanRxBuffer0Command2::
	.blkb 13
	.dbsym e CanRxBuffer0Command2 _CanRxBuffer0Command2 A[13:13]c
_CanRxBuffer0Command1::
	.blkb 13
	.dbsym e CanRxBuffer0Command1 _CanRxBuffer0Command1 A[13:13]c
_CanRxBuffer0Command0::
	.blkb 13
	.dbsym e CanRxBuffer0Command0 _CanRxBuffer0Command0 A[13:13]c
_CanRxBuffer0::
	.blkb 104
	.dbsym e CanRxBuffer0 _CanRxBuffer0 A[104:8:13]c
_OutputByte2Reg::
	.blkb 1
	.dbsym e OutputByte2Reg _OutputByte2Reg c
_OutputByte1Reg::
	.blkb 1
	.dbsym e OutputByte1Reg _OutputByte1Reg c
_OutputByte0Reg::
	.blkb 1
	.dbsym e OutputByte0Reg _OutputByte0Reg c
_RxBuffer0::
	.blkb 256
	.dbsym e RxBuffer0 _RxBuffer0 A[256:256]c
_TxBuffer0::
	.blkb 256
	.dbsym e TxBuffer0 _TxBuffer0 A[256:256]c